gdb/riscv: Add target description support

This commit adds target description support for riscv.

I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.

If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.

This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description.  Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.

I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.

This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently.  We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort).  The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.

	* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
	(HFILES_NO_SRCDIR): Add arch/riscv.h.
	* arch/riscv.c: New file.
	* arch/riscv.h: New file.
	* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
	this list, and add arch/riscv.o.
	* features/Makefile: Add riscv features.
	* features/riscv/32bit-cpu.c: New file.
	* features/riscv/32bit-cpu.xml: New file.
	* features/riscv/32bit-csr.c: New file.
	* features/riscv/32bit-csr.xml: New file.
	* features/riscv/32bit-fpu.c: New file.
	* features/riscv/32bit-fpu.xml: New file.
	* features/riscv/64bit-cpu.c: New file.
	* features/riscv/64bit-cpu.xml: New file.
	* features/riscv/64bit-csr.c: New file.
	* features/riscv/64bit-csr.xml: New file.
	* features/riscv/64bit-fpu.c: New file.
	* features/riscv/64bit-fpu.xml: New file.
	* features/riscv/rebuild-csr-xml.sh: New file.
	* riscv-tdep.c: Add 'arch/riscv.h' include.
	(riscv_gdb_reg_names): Delete.
	(csr_reggroup): New global.
	(struct riscv_register_alias): Delete.
	(struct riscv_register_feature): New structure.
	(riscv_register_aliases): Delete.
	(riscv_xreg_feature): New global.
	(riscv_freg_feature): New global.
	(riscv_virtual_feature): New global.
	(riscv_csr_feature): New global.
	(riscv_create_csr_aliases): New function.
	(riscv_read_misa_reg): Delete.
	(riscv_has_feature): Delete.
	(riscv_isa_xlen): Simplify, just return cached xlen.
	(riscv_isa_flen): Simplify, just return cached flen.
	(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
	(riscv_register_name): Update to make use of tdesc_register_name.
	Look up xreg and freg names in the new globals riscv_xreg_feature
	and riscv_freg_feature.  Don't supply csr aliases here.
	(riscv_fpreg_q_type): Delete.
	(riscv_register_type): Use tdesc_register_type in almost all
	cases, override the returned type in a few specific cases only.
	(riscv_print_one_register_info): Handle errors reading registers.
	(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
	registers that are otherwise unknown to GDB.  Also check the
	csr_reggroup.
	(riscv_print_registers_info): Remove assert about upper register
	number, and use gdbarch_register_reggroup_p instead of
	short-cutting.
	(riscv_find_default_target_description): New function.
	(riscv_check_tdesc_feature): New function.
	(riscv_add_reggroups): New function.
	(riscv_setup_register_aliases): New function.
	(riscv_init_reggroups): New function.
	(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
	setup register groups.  Register new riscv debug variable.
	* riscv-tdep.h: Add 'arch/riscv.h' include.
	(struct gdbarch_tdep): Remove abi union, and add
	riscv_gdbarch_features field.  Remove cached quad floating point
	type, and provide initialisation for double type field.
	* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
	the list of targets using the feature based target descriptions.
	* NEWS: Mention target description support.

gdb/doc/ChangeLog:

	* gdb.texinfo (Standard Target Features): Add RISC-V Features
	sub-section.

2 files changed, 133 insertions, 0 deletions

diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c
new file mode 100644
index 0000000..ca2238d
--- /dev/null
+++ b/gdb/arch/riscv.c
@@ -0,0 +1,69 @@
+/* Copyright (C) 2018 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "common-defs.h"
+#include "riscv.h"
+#include <stdlib.h>
+
+#include "../features/riscv/32bit-cpu.c"
+#include "../features/riscv/64bit-cpu.c"
+#include "../features/riscv/32bit-fpu.c"
+#include "../features/riscv/64bit-fpu.c"
+
+/* See arch/riscv.h.  */
+
+target_desc *
+riscv_create_target_description (struct riscv_gdbarch_features features)
+{
+  target_desc *tdesc = allocate_target_description ();
+
+#ifndef IN_PROCESS_AGENT
+  std::string arch_name = "riscv";
+
+  if (features.xlen == 4)
+    arch_name.append (":rv32i");
+  else if (features.xlen == 8)
+    arch_name.append (":rv64i");
+  else if (features.xlen == 16)
+    arch_name.append (":rv128i");
+
+  if (features.flen == 4)
+    arch_name.append ("f");
+  else if (features.flen == 8)
+    arch_name.append ("d");
+  else if (features.flen == 16)
+    arch_name.append ("q");
+
+  set_tdesc_architecture (tdesc, arch_name.c_str ());
+#endif
+
+  long regnum = 0;
+
+  /* For now we only support creating 32-bit or 64-bit x-registers.  */
+  if (features.xlen == 4)
+    regnum = create_feature_riscv_32bit_cpu (tdesc, regnum);
+  else if (features.xlen == 8)
+    regnum = create_feature_riscv_64bit_cpu (tdesc, regnum);
+
+  /* For now we only support creating 32-bit or 64-bit f-registers.  */
+  if (features.flen == 4)
+    regnum = create_feature_riscv_32bit_fpu (tdesc, regnum);
+  else if (features.flen == 8)
+    regnum = create_feature_riscv_64bit_fpu (tdesc, regnum);
+
+  return tdesc;
+}
diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
new file mode 100644
index 0000000..0079440
--- /dev/null
+++ b/gdb/arch/riscv.h
@@ -0,0 +1,64 @@
+/* Common target-dependent functionality for RISC-V
+
+   Copyright (C) 2018 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef ARCH_RISCV_H
+#define ARCH_RISCV_H
+
+#include "common/tdesc.h"
+
+/* The set of RISC-V architectural features that we track that impact how
+   we configure the actual gdbarch instance.  We hold one of these in the
+   gdbarch_tdep structure, and use it to distinguish between different
+   RISC-V gdbarch instances.
+
+   The information in here ideally comes from the target description,
+   however, if the target doesn't provide a target description then we will
+   create a default target description by first populating one of these
+   based on what we know about the binary being executed, and using that to
+   drive default target description creation.  */
+
+struct riscv_gdbarch_features
+{
+  /* The size of the x-registers in bytes.  This is either 4 (RV32), 8
+     (RV64), or 16 (RV128).  No other value is valid.  Initialise to the
+     invalid 0 value so we can spot if one of these is used
+     uninitialised.  */
+  int xlen = 0;
+
+  /* The size of the f-registers in bytes.  This is either 4 (RV32), 8
+     (RV64), or 16 (RV128).  This can also hold the value 0 to indicate
+     that there are no f-registers.  No other value is valid.  */
+  int flen = 0;
+
+  /* This indicates if hardware floating point abi is in use.  If the FLEN
+     field is 0 then this value _must_ be false.  If the FLEN field is
+     non-zero and this field is false then this indicates the target has
+     floating point registers, but is still using the soft-float abi.  If
+     this field is true then the hardware floating point abi is in use, and
+     values are passed in f-registers matching the size of FLEN.  */
+  bool hw_float_abi = false;
+};
+
+/* Create and return a target description that is compatible with
+   FEATURES.  */
+
+target_desc *riscv_create_target_description
+	(struct riscv_gdbarch_features features);
+
+#endif /* ARCH_RISCV_H */