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authorYao Qi <yao.qi@linaro.org>2016-09-16 14:58:31 +0100
committerYao Qi <yao.qi@linaro.org>2016-09-21 12:29:53 +0100
commitfc6cda2ee85d2c2719db3b5ae3a1ae963f28416b (patch)
tree6fffa61c201da1162d729cd919d3fc5608d1d70d /gdb/aarch32-linux-nat.c
parent44b8317a75390fd3713da6d8cc0f593c041fd8a2 (diff)
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Keep reserved bits in CPSR on write
In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html I cleared reserved bits when reading CPSR. It makes a problem that these bits (zero) are written back to kernel through ptrace, and it changes the state of the processor on some recent kernel, which is unexpected. In this patch, I keep these reserved bits when write CPSR back to hardware. gdb: 2016-09-21 Yao Qi <yao.qi@linaro.org> * aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep bits 20 to 23. gdb/gdbserver: 2016-09-21 Yao Qi <yao.qi@linaro.org> * linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to 23.
Diffstat (limited to 'gdb/aarch32-linux-nat.c')
-rw-r--r--gdb/aarch32-linux-nat.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/gdb/aarch32-linux-nat.c b/gdb/aarch32-linux-nat.c
index 72bf644..2df672d 100644
--- a/gdb/aarch32-linux-nat.c
+++ b/gdb/aarch32-linux-nat.c
@@ -67,8 +67,15 @@ aarch32_gp_regcache_collect (const struct regcache *regcache, uint32_t *regs,
if (arm_apcs_32
&& REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM))
- regcache_raw_collect (regcache, ARM_PS_REGNUM,
- &regs[ARM_CPSR_GREGNUM]);
+ {
+ uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
+
+ regcache_raw_collect (regcache, ARM_PS_REGNUM,
+ &regs[ARM_CPSR_GREGNUM]);
+ /* Keep reserved bits bit 20 to bit 23. */
+ regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
+ | (cpsr & 0x00f00000));
+ }
}
/* Supply VFP registers contents, stored in REGS, to REGCACHE.