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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-30 01:04:42 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-30 04:00:40 +0000 |
| commit | fe0f44a0caf59db09ad4bc16a46926aba96ce60d (patch) | |
| tree | 745bdcb298f35b3441dfc52ea3455fb225e15b49 /gas | |
| parent | aa1e22eb8d685d456469f3da7933f9215b4d79ef (diff) | |
| download | binutils-fe0f44a0caf59db09ad4bc16a46926aba96ce60d.zip binutils-fe0f44a0caf59db09ad4bc16a46926aba96ce60d.tar.gz binutils-fe0f44a0caf59db09ad4bc16a46926aba96ce60d.tar.bz2 | |
RISC-V: Make XVentanaCondOps RV64 only
Although XVentanaCondOps instructions are XLEN-agonistic, Ventana's manual
only defines them only for RV64 (because all Ventana's processors implement
RV64).
This commit limits XVentanaCondOps instructions RV64-only to match the
behavior of the manual and LLVM.
Note that this commit alone will not make XVentanaCondOps extension with
RV32 invalid (it just makes XVentanaCondOps on RV32 empty).
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Restrict "vt.maskc" and "vt.maskcn"
to XLEN=64.
gas/ChangeLog:
* testsuite/gas/riscv/x-ventana-condops-32.d: New failure test.
* testsuite/gas/riscv/x-ventana-condops-32.l: Likewise.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/riscv/x-ventana-condops-32.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-ventana-condops-32.l | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/x-ventana-condops-32.d b/gas/testsuite/gas/riscv/x-ventana-condops-32.d new file mode 100644 index 0000000..ea67515 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-ventana-condops-32.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_xventanacondops +#source: x-ventana-condops.s +#error_output: x-ventana-condops-32.l diff --git a/gas/testsuite/gas/riscv/x-ventana-condops-32.l b/gas/testsuite/gas/riscv/x-ventana-condops-32.l new file mode 100644 index 0000000..e434caf --- /dev/null +++ b/gas/testsuite/gas/riscv/x-ventana-condops-32.l @@ -0,0 +1,3 @@ +.*Assembler messages: +.*Error: unrecognized opcode `vt.maskc a0,a1,a2' +.*Error: unrecognized opcode `vt.maskcn a0,a3,a4' |