[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7

Armv8.7 architecture introduces the "accelerator extension", aka
load/store of 64 bytes. New atomic load/store instructions are: LD64B,
ST64B, ST64BV and ST64BV0.

This patch adds:
+ New feature +ls64 to -march command line.
+ New atomic load/store instructions associated with above feature.

For more details regarding atomic 64-byte load/store instruction for
Armv8.7 please refer to Arm A64 Instruction set documentation for
Armv8-A architecture profile, see document page 157 for load
instruction, and pages 414-418 for store instructions of [0].

    [0]: https://developer.arm.com/docs/ddi0596/i

7 files changed, 76 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7753285..bb6660f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2020-11-03  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+	* NEWS: Update docs.
+	* config/tc-aarch64.c: Add +ls64 feature to -march flags set.
+	* testsuite/gas/aarch64/ls64-invalid.d: New test.
+	* testsuite/gas/aarch64/ls64-invalid.l: New test.
+	* testsuite/gas/aarch64/ls64-invalid.s: New test.
+	* testsuite/gas/aarch64/ls64.s: New test.
+
 2020-11-03  Christian Eggers  <ceggers@gmx.de>
 
 	* config/obj-elf (elf_frob_symbol): Fix symbol value calculation
diff --git a/gas/NEWS b/gas/NEWS
index 928db98..8841507 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -27,6 +27,9 @@
 * Add support for +csre feature for -march. Add CSR PDEC instruction for CSRE
   feature.
 
+* Add support for +ls64 feature for -march in Armv8.7 AArch64. Add atomic
+  64-byte load/store instructions for this feature.
+
 * Add support for Intel TDX instructions.
 
 * Add support for Intel Key Locker instructions.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 930a00c..73600e2 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -9206,6 +9206,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
   {"csre",		AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0),
 			AARCH64_ARCH_NONE},
+  {"ls64",		AARCH64_FEATURE (AARCH64_FEATURE_LS64, 0),
+			AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
diff --git a/gas/testsuite/gas/aarch64/ls64-invalid.d b/gas/testsuite/gas/aarch64/ls64-invalid.d
new file mode 100644
index 0000000..69e739d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ls64-invalid.d
@@ -0,0 +1,3 @@
+#name: Atomic 64-byte load/store instruction
+#source: ls64-invalid.s
+#error_output: ls64-invalid.l
diff --git a/gas/testsuite/gas/aarch64/ls64-invalid.l b/gas/testsuite/gas/aarch64/ls64-invalid.l
new file mode 100644
index 0000000..64b6e58
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ls64-invalid.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support `ld64b x0,\[x1\]'
+.*: Error: selected processor does not support `st64b x0,\[x1\]'
+.*: Error: selected processor does not support `st64bv x0,x1,\[x2\]'
+.*: Error: selected processor does not support `st64bv0 x0,x1,\[x2\]'
diff --git a/gas/testsuite/gas/aarch64/ls64-invalid.s b/gas/testsuite/gas/aarch64/ls64-invalid.s
new file mode 100644
index 0000000..8c89aaf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ls64-invalid.s
@@ -0,0 +1,14 @@
+/* Atomic 64-byte load/store instructions require Armv8.7-a extension.  */
+.arch armv8.6-a
+
+/* Single-copy Atomic 64-byte Load.  */
+	ld64b x0, [x1]
+
+/* Single-copy Atomic 64-byte Store without Return.  */
+	st64b x0, [x1]
+
+/* Single-copy Atomic 64-byte Store with Return.  */
+	st64bv x0, x1, [x2]
+
+/* Single-copy Atomic 64-byte EL0 Store with Return.  */
+	st64bv0 x0, x1, [x2]
diff --git a/gas/testsuite/gas/aarch64/ls64.s b/gas/testsuite/gas/aarch64/ls64.s
new file mode 100644
index 0000000..efbd0bf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ls64.s
@@ -0,0 +1,40 @@
+/* Atomic 64-byte load/store instructions.  */
+.arch armv8.7-a+ls64
+
+/* Single-copy Atomic 64-byte Load.  */
+	ld64b x0, [x1]
+	ld64b x1, [x2]
+	ld64b x2, [x4]
+	ld64b x4, [x8]
+	ld64b x8, [x16]
+	ld64b x16, [x1]
+	ld64b x16, [sp]
+
+/* Single-copy Atomic 64-byte Store without Return.  */
+	st64b x0, [x1]
+	st64b x1, [x2]
+	st64b x2, [x4]
+	st64b x4, [x8]
+	st64b x8, [x16]
+	st64b x16, [x1]
+	st64b x16, [sp]
+
+/* Single-copy Atomic 64-byte Store with Return.  */
+	st64bv x0, x1, [x2]
+	st64bv x1, x2, [x4]
+	st64bv x2, x4, [x8]
+	st64bv x4, x8, [x16]
+	st64bv x8, x16, [x30]
+	st64bv x16, x30, [x0]
+	st64bv x30, x1, [x2]
+	st64bv x30, x1, [sp]
+
+/* Single-copy Atomic 64-byte EL0 Store with Return.  */
+	st64bv0 x0, x1, [x2]
+	st64bv0 x1, x2, [x4]
+	st64bv0 x2, x4, [x8]
+	st64bv0 x4, x8, [x16]
+	st64bv0 x8, x16, [x30]
+	st64bv0 x16, x30, [x0]
+	st64bv0 x30, x1, [x2]
+	st64bv0 x30, x1, [sp]