2012-09-11 Chris Schlumberger-Socha <chris.schlumberger-socha@arm.com>

	bfd/

	* bfd-in2.h: Regenerated.
	* elf64-aarch64.c
	(elf64_aarch64_howto_table): Add R_AARCH64_GOT_LD_PREL19 reloc to HOWTO.
	(elf64_aarch64_reloc_map): Add reloc entry.
	(aarch64_resolve_relocation): Likewise.
	(bfd_elf_aarch64_put_addend): Likewise.
	(aarch64_reloc_got_type): Likewise.
	(elf64_aarch64_final_link_relocate): Likewise.
	(lf64_aarch64_check_relocs): Likewise.
	(elf64_aarch64_check_relocs): New case for R_AARCH64_ADR_PREL_LO21
	reloc.
	* libbfd.h: Regenerated.
	* reloc.c (R_AARCH64_GOT_LD_PREL19): New reloc.

	gas/

	* config/tc-aarch64.c
	(reloc_table): Add reloc to table entry.
	(parse_address_main): Add support for #:<reloc_op>:<symbol>.
	(parse_operands): Check for unused reloc.
	(md_apply_fix): New case for reloc.
	(aarch64_force_relocation): Likewise.

	gas/testsuite

	* gas/aarch64/reloc-insn.d
	(BFD_RELOC_AARCH64_GOT_LD_PREL19): Add expected asm for new reloc test.
	* gas/aarch64/reloc-insn.s
	(BFD_RELOC_AARCH64_GOT_LD_PREL19): Add test for reloc.

	include/

	* elf/aarch64.h (R_AARCH64_GOT_LD_PREL19): New reloc.

	ld/testsuite

	* ld-aarch64/aarch64-elf.exp: New reloc tests.
	* ld-aarch64/emit-relocs-309-low-bad.d: New file. Expected asm for test
	failure (lower bound overflow).
	* ld-aarch64/emit-relocs-309-low.d: New file. Expected asm for test
	success (lower bound).
	* ld-aarch64/emit-relocs-309-up-bad.d: New file. Expected asm for test
	failure (upper bound overflow).
	* ld-aarch64/emit-relocs-309-up.d: New file. Expected asm for test
	success (upper bound).
	* ld-aarch64/emit-relocs-309.s: New file. Asm for new reloc tests.

5 files changed, 127 insertions, 53 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b1004d2..0304941 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2012-09-12  Chris Schlumberger-Socha  <chris.schlumberger-socha@arm.com>
+
+	* config/tc-aarch64.c
+	(reloc_table): Add reloc to table entry.
+	(parse_address_main): Add support for #:<reloc_op>:<symbol>.
+	(parse_operands): Check for unused reloc.
+	(md_apply_fix): New case for reloc.
+	(aarch64_force_relocation): Likewise.
 
 2012-09-11  Georg-Johann Lay  <avr@gjlay.de>
 
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 4333e8e..e695e88 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -2298,6 +2298,12 @@ static struct reloc_table_entry reloc_table[] = {
    BFD_RELOC_AARCH64_MOVW_G3,
    0,
    0},
+  /* Get to the GOT entry for a symbol.  */
+  {"got_prel19", 0,
+   0,
+   0,
+   0,
+   BFD_RELOC_AARCH64_GOT_LD_PREL19},
   /* Get to the page containing GOT entry for a symbol.  */
   {"got", 1,
    BFD_RELOC_AARCH64_ADR_GOT_PAGE,
@@ -2816,14 +2822,53 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
       operand->addr.pcrel = 1;
       operand->addr.preind = 1;
 
-      if (skip_past_char (&p, '='))
-	/* =immediate; need to generate the literal in the liternal pool.  */
-	inst.gen_lit_pool = 1;
+      /* #:<reloc_op>:<symbol>  */
+      skip_past_char (&p, '#');
+      if (reloc && skip_past_char (&p, ':'))
+	{
+	  struct reloc_table_entry *entry;
+
+	  /* Try to parse a relocation modifier.  Anything else is
+	     an error.  */
+	  entry = find_reloc_table_entry (&p);
+	  if (! entry)
+	    {
+	      set_syntax_error (_("unknown relocation modifier"));
+	      return FALSE;
+	    }
+
+	  if (entry->ldst_type == 0)
+	    {
+	      set_syntax_error
+		(_("this relocation modifier is not allowed on this "
+		   "instruction"));
+	      return FALSE;
+	    }
+
+	  /* #:<reloc_op>:  */
+	  if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
+	    {
+	      set_syntax_error (_("invalid relocation expression"));
+	      return FALSE;
+	    }
 
-      if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
+	  /* #:<reloc_op>:<expr>  */
+	  /* Record the load/store relocation type.  */
+	  inst.reloc.type = entry->ldst_type;
+	  inst.reloc.pc_rel = entry->pc_rel;
+	}
+      else
 	{
-	  set_syntax_error (_("invalid address"));
-	  return FALSE;
+
+	  if (skip_past_char (&p, '='))
+	    /* =immediate; need to generate the literal in the literal pool. */
+	    inst.gen_lit_pool = 1;
+
+	  if (!my_get_expression (exp, &p, GE_NO_PREFIX, 1))
+	    {
+	      set_syntax_error (_("invalid address"));
+	      return FALSE;
+	    }
 	}
 
       *str = p;
@@ -4889,37 +4934,39 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  else
 	    {
 	      info->imm.value = 0;
-	      switch (opcode->iclass)
-		{
-		case compbranch:
-		case condbranch:
-		  /* e.g. CBZ or B.COND  */
-		  gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
-		  inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
-		  break;
-		case testbranch:
-		  /* e.g. TBZ  */
-		  gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
-		  inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
-		  break;
-		case branch_imm:
-		  /* e.g. B or BL  */
-		  gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
-		  inst.reloc.type = (opcode->op == OP_BL)
-		    ? BFD_RELOC_AARCH64_CALL26 : BFD_RELOC_AARCH64_JUMP26;
-		  break;
-		case loadlit:
-		  gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
-		  inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
-		  break;
-		case pcreladdr:
-		  gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
-		  inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
-		  break;
-		default:
-		  gas_assert (0);
-		  abort ();
-		}
+	      if (inst.reloc.type == BFD_RELOC_UNUSED)
+		switch (opcode->iclass)
+		  {
+		  case compbranch:
+		  case condbranch:
+		    /* e.g. CBZ or B.COND  */
+		    gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
+		    inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
+		    break;
+		  case testbranch:
+		    /* e.g. TBZ  */
+		    gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
+		    inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
+		    break;
+		  case branch_imm:
+		    /* e.g. B or BL  */
+		    gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
+		    inst.reloc.type =
+		      (opcode->op == OP_BL) ? BFD_RELOC_AARCH64_CALL26
+			 : BFD_RELOC_AARCH64_JUMP26;
+		    break;
+		  case loadlit:
+		    gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
+		    inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
+		    break;
+		  case pcreladdr:
+		    gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
+		    inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
+		    break;
+		  default:
+		    gas_assert (0);
+		    abort ();
+		  }
 	      inst.reloc.pc_rel = 1;
 	    }
 	  break;
@@ -6418,6 +6465,7 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
     case BFD_RELOC_AARCH64_LDST32_LO12:
     case BFD_RELOC_AARCH64_LDST64_LO12:
     case BFD_RELOC_AARCH64_LDST128_LO12:
+    case BFD_RELOC_AARCH64_GOT_LD_PREL19:
     case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
     case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
       /* Should always be exported to object file, see
@@ -6575,6 +6623,7 @@ aarch64_force_relocation (struct fix *fixp)
     case BFD_RELOC_AARCH64_LDST32_LO12:
     case BFD_RELOC_AARCH64_LDST64_LO12:
     case BFD_RELOC_AARCH64_LDST128_LO12:
+    case BFD_RELOC_AARCH64_GOT_LD_PREL19:
       /* Always leave these relocations for the linker.  */
       return 1;
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 56b7eda..d2d3d84 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2012-09-12  Chris Schlumberger-Socha  <chris.schlumberger-socha@arm.com>
+
+	* gas/aarch64/reloc-insn.d
+	(BFD_RELOC_AARCH64_GOT_LD_PREL19): Add expected asm for new reloc test.
+	* gas/aarch64/reloc-insn.s
+	(BFD_RELOC_AARCH64_GOT_LD_PREL19): Add test for reloc.
+
 2012-09-04  Sergey A. Guriev  <sergey.a.guriev@intel.com>
 
 	* gas/testsuite/gas/ia64/psn.d: New file.
diff --git a/gas/testsuite/gas/aarch64/reloc-insn.d b/gas/testsuite/gas/aarch64/reloc-insn.d
index ce37b92..7eb13a2 100644
--- a/gas/testsuite/gas/aarch64/reloc-insn.d
+++ b/gas/testsuite/gas/aarch64/reloc-insn.d
@@ -37,12 +37,12 @@ Disassembly of section \.text:
   5c:	f2d75301 	movk	x1, #0xba98, lsl #32
   60:	f2aeca81 	movk	x1, #0x7654, lsl #16
   64:	f2864201 	movk	x1, #0x3210
-  68:	58000920 	ldr	x0, 18c <llit>
+  68:	58000960 	ldr	x0, 194 <llit>
   6c:	58000001 	ldr	x1, 0 <func>
 			6c: R_AARCH64_LD_PREL_LO19	\.data\+0x8
   70:	58000002 	ldr	x2, 0 <xdata>
 			70: R_AARCH64_LD_PREL_LO19	xdata\+0xc
-  74:	100008c0 	adr	x0, 18c <llit>
+  74:	10000900 	adr	x0, 194 <llit>
   78:	10000001 	adr	x1, 0 <func>
 			78: R_AARCH64_ADR_PREL_LO21	\.data\+0x8
   7c:	10000002 	adr	x2, 0 <func>
@@ -54,7 +54,7 @@ Disassembly of section \.text:
   88:	10000005 	adr	x5, 0 <xdata>
 			88: R_AARCH64_ADR_PREL_LO21	xdata\+0xff8
   8c:	90000000 	adrp	x0, 0 <func>
-			8c: R_AARCH64_ADR_PREL_PG_HI21	\.text\+0x18c
+			8c: R_AARCH64_ADR_PREL_PG_HI21	\.text\+0x194
   90:	90000001 	adrp	x1, 0 <func>
 			90: R_AARCH64_ADR_PREL_PG_HI21	\.data\+0x8
   94:	90000002 	adrp	x2, 0 <func>
@@ -66,7 +66,7 @@ Disassembly of section \.text:
   a0:	90000005 	adrp	x5, 0 <xdata>
 			a0: R_AARCH64_ADR_PREL_PG_HI21	xdata\+0xff8
   a4:	90000000 	adrp	x0, 0 <func>
-			a4: R_AARCH64_ADR_PREL_PG_HI21	\.text\+0x18c
+			a4: R_AARCH64_ADR_PREL_PG_HI21	\.text\+0x194
   a8:	90000001 	adrp	x1, 0 <func>
 			a8: R_AARCH64_ADR_PREL_PG_HI21	\.data\+0x8
   ac:	90000002 	adrp	x2, 0 <func>
@@ -78,7 +78,7 @@ Disassembly of section \.text:
   b8:	90000005 	adrp	x5, 0 <xdata>
 			b8: R_AARCH64_ADR_PREL_PG_HI21	xdata\+0xff8
   bc:	91000000 	add	x0, x0, #0x0
-			bc: R_AARCH64_ADD_ABS_LO12_NC	\.text\+0x18c
+			bc: R_AARCH64_ADD_ABS_LO12_NC	\.text\+0x194
   c0:	91000021 	add	x1, x1, #0x0
 			c0: R_AARCH64_ADD_ABS_LO12_NC	\.data\+0x8
   c4:	91000042 	add	x2, x2, #0x0
@@ -91,7 +91,7 @@ Disassembly of section \.text:
 			d0: R_AARCH64_ADD_ABS_LO12_NC	xdata\+0xff8
   d4:	913ffcc6 	add	x6, x6, #0xfff
   d8:	39400000 	ldrb	w0, \[x0\]
-			d8: R_AARCH64_LDST8_ABS_LO12_NC	\.text\+0x18c
+			d8: R_AARCH64_LDST8_ABS_LO12_NC	\.text\+0x194
   dc:	39400021 	ldrb	w1, \[x1\]
 			dc: R_AARCH64_LDST8_ABS_LO12_NC	\.data\+0x8
   e0:	39400042 	ldrb	w2, \[x2\]
@@ -103,22 +103,22 @@ Disassembly of section \.text:
   ec:	394000a5 	ldrb	w5, \[x5\]
 			ec: R_AARCH64_LDST8_ABS_LO12_NC	xdata\+0xff8
   f0:	397ffcc6 	ldrb	w6, \[x6,#4095\]
-  f4:	360004e0 	tbz	w0, #0, 190 <lab>
+  f4:	36000520 	tbz	w0, #0, 198 <lab>
   f8:	b6f80001 	tbz	x1, #63, 0 <xlab>
 			f8: R_AARCH64_TSTBR14	xlab
-  fc:	374004a2 	tbnz	w2, #8, 190 <lab>
+  fc:	374004e2 	tbnz	w2, #8, 198 <lab>
  100:	b7780002 	tbnz	x2, #47, 0 <xlab>
 			100: R_AARCH64_TSTBR14	xlab
- 104:	54000460 	b\.eq	190 <lab>
+ 104:	540004a0 	b\.eq	198 <lab>
  108:	54000000 	b\.eq	0 <xlab>
 			108: R_AARCH64_CONDBR19	xlab
- 10c:	b4000420 	cbz	x0, 190 <lab>
+ 10c:	b4000460 	cbz	x0, 198 <lab>
  110:	b500001e 	cbnz	x30, 0 <xlab>
 			110: R_AARCH64_CONDBR19	xlab
- 114:	1400001f 	b	190 <lab>
+ 114:	14000021 	b	198 <lab>
  118:	14000000 	b	0 <xlab>
 			118: R_AARCH64_JUMP26	xlab
- 11c:	9400001d 	bl	190 <lab>
+ 11c:	9400001f 	bl	198 <lab>
  120:	94000000 	bl	0 <xlab>
 			120: R_AARCH64_CALL26	xlab
  124:	d2e24680 	movz	x0, #0x1234, lsl #48
@@ -142,7 +142,7 @@ Disassembly of section \.text:
  16c:	f8500020 	ldr	x0, \[x1,#-256\]
  170:	f97ffc20 	ldr	x0, \[x1,#32760\]
  174:	79400000 	ldrh	w0, \[x0\]
-			174: R_AARCH64_LDST16_ABS_LO12_NC	\.text\+0x18c
+			174: R_AARCH64_LDST16_ABS_LO12_NC	\.text\+0x194
  178:	b9400021 	ldr	w1, \[x1\]
 			178: R_AARCH64_LDST32_ABS_LO12_NC	\.data\+0x8
  17c:	f9400042 	ldr	x2, \[x2\]
@@ -151,7 +151,11 @@ Disassembly of section \.text:
 			180: R_AARCH64_LDST128_ABS_LO12_NC	xlit
  184:	f98000f0 	prfm	pstl1keep, \[x7\]
 			184: R_AARCH64_LDST64_ABS_LO12_NC	\.data\+0x100c
- 188:	d65f03c0 	ret
+ 188:	58000000 	ldr	x0, 1 <func\+0x1>
+			188: R_AARCH64_GOT_LD_PREL19	cdata
+ 18c:	39400001 	ldrb	w1, \[x0\]
+ 190:	d65f03c0 	ret
 
-000000000000018c <llit>:
- 18c:	deadf00d 	\.word	0xdeadf00d
+
+0000000000000194 <llit>:
+ 194:	deadf00d 	\.word	0xdeadf00d
diff --git a/gas/testsuite/gas/aarch64/reloc-insn.s b/gas/testsuite/gas/aarch64/reloc-insn.s
index d6e6aa6..1d13900 100644
--- a/gas/testsuite/gas/aarch64/reloc-insn.s
+++ b/gas/testsuite/gas/aarch64/reloc-insn.s
@@ -176,6 +176,10 @@ func:
 
 	// BFD_RELOC_AARCH64_LDST64_LO12
 	prfm	pstl1keep, [x7, #:lo12:ldata+4100]
+
+	// BFD_RELOC_AARCH64_GOT_LD_PREL19
+	ldr	x0, :got_prel19:cdata
+	ldrb	w1, [x0]
 	
 	ret
 	
@@ -201,3 +205,5 @@ ldata:	.xword	0x1122334455667788
 .set u64, 0xfedcba9876543210
 .set bit1,0xf000000000000000
 .set bit2,~0xf
+
+.comm	cdata,1,8