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| author | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 09:42:56 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 09:42:56 +0100 |
| commit | dec718565a5cc22f3664c552d5618fdf21480c10 (patch) | |
| tree | a1df176ac3ef43130e0fc30395eff76086ab55fc /gas | |
| parent | b734aebe68e2db7e03eece1ae83467ef5d4391f1 (diff) | |
| download | binutils-dec718565a5cc22f3664c552d5618fdf21480c10.zip binutils-dec718565a5cc22f3664c552d5618fdf21480c10.tar.gz binutils-dec718565a5cc22f3664c552d5618fdf21480c10.tar.bz2 | |
MIPS/GAS/testsuite: Also verify trap expansions of division macros
Provide 'div' test variants for trap expansions as requested by the
'-trap' command-line option, and run them across all the compatible
architectures.
Diffstat (limited to 'gas')
20 files changed, 418 insertions, 0 deletions
diff --git a/gas/testsuite/gas/mips/allegrex@div-trap.d b/gas/testsuite/gas/mips/allegrex@div-trap.d new file mode 100644 index 0000000..2000416 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses +#name: MIPS div with traps +#source: div.s +#dump: div.d diff --git a/gas/testsuite/gas/mips/div-trap.d b/gas/testsuite/gas/mips/div-trap.d new file mode 100644 index 0000000..5a76586 --- /dev/null +++ b/gas/testsuite/gas/mips/div-trap.d @@ -0,0 +1,80 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS div with traps +#source: div.s + +# Test the div macro. + +.*: +file format .*mips.* + +Disassembly of section .text: +[0-9a-f]+ <[^>]*> 0085001a div zero,a0,a1 +[0-9a-f]+ <[^>]*> 00a001f4 teq a1,zero,0x7 +[0-9a-f]+ <[^>]*> 0085001a div zero,a0,a1 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14a10002 bne a1,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 008101b4 teq a0,at,0x6 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00c001f4 teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00a6001a div zero,a1,a2 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14c10002 bne a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 00a101b4 teq a1,at,0x6 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00802025 move a0,a0 +[0-9a-f]+ <[^>]*> 00a02025 move a0,a1 +[0-9a-f]+ <[^>]*> 00042022 neg a0,a0 +[0-9a-f]+ <[^>]*> 00052022 neg a0,a1 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 34018000 li at,0x8000 +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 34018000 li at,0x8000 +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 24018000 li at,-32768 +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 24018000 li at,-32768 +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1 +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1 +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1 +[0-9a-f]+ <[^>]*> 3421a5a5 ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1 +[0-9a-f]+ <[^>]*> 3421a5a5 ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 0085001b divu zero,a0,a1 +[0-9a-f]+ <[^>]*> 00a001f4 teq a1,zero,0x7 +[0-9a-f]+ <[^>]*> 0085001b divu zero,a0,a1 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00c001f4 teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00a6001b divu zero,a1,a2 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00802025 move a0,a0 +[0-9a-f]+ <[^>]*> 00c001f4 teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00a6001a div zero,a1,a2 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14c10002 bne a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 00a101b4 teq a1,at,0x6 +[0-9a-f]+ <[^>]*> 00002010 mfhi a0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00a1001b divu zero,a1,at +[0-9a-f]+ <[^>]*> 00002010 mfhi a0 + \.\.\. diff --git a/gas/testsuite/gas/mips/div64-trap.d b/gas/testsuite/gas/mips/div64-trap.d new file mode 100644 index 0000000..eab1975 --- /dev/null +++ b/gas/testsuite/gas/mips/div64-trap.d @@ -0,0 +1,28 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS 64-bit div with traps +#source: div64.s + +# Test the div macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 00c001f4 teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00a6001e ddiv zero,a1,a2 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14c10003 bne a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 24010001 li at,1 +[0-9a-f]+ <[^>]*> 00010ffc dsll32 at,at,0x1f +[0-9a-f]+ <[^>]*> 00a101b4 teq a1,at,0x6 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00a1001f ddivu zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 34018000 li at,0x8000 +[0-9a-f]+ <[^>]*> 00a1001e ddiv zero,a1,at +[0-9a-f]+ <[^>]*> 00002010 mfhi a0 +[0-9a-f]+ <[^>]*> 24018000 li at,-32768 +[0-9a-f]+ <[^>]*> 00a1001f ddivu zero,a1,at +[0-9a-f]+ <[^>]*> 00002010 mfhi a0 + \.\.\. diff --git a/gas/testsuite/gas/mips/micromips@div-trap.d b/gas/testsuite/gas/mips/micromips@div-trap.d new file mode 100644 index 0000000..bd157bd --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@div-trap.d @@ -0,0 +1,83 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS div with traps +#source: div.s + +# Test the div macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 00a4 ab3c div zero,a0,a1 +[0-9a-f]+ <[^>]*> 0005 703c teq a1,zero,0x7 +[0-9a-f]+ <[^>]*> 00a4 ab3c div zero,a0,a1 +[0-9a-f]+ <[^>]*> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b425 fffe bne a1,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_0 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 0024 603c teq a0,at,0x6 +[0-9a-f]+ <\.L\^_0> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 0006 703c teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00c5 ab3c div zero,a1,a2 +[0-9a-f]+ <[^>]*> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b426 fffe bne a2,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_1 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 0025 603c teq a1,at,0x6 +[0-9a-f]+ <\.L\^_1> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 0c84 move a0,a0 +[0-9a-f]+ <[^>]*> 0c85 move a0,a1 +[0-9a-f]+ <[^>]*> 0080 2190 neg a0,a0 +[0-9a-f]+ <[^>]*> 00a0 2190 neg a0,a1 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0024 ab3c div zero,a0,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0025 ab3c div zero,a1,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000 +[0-9a-f]+ <[^>]*> 0024 ab3c div zero,a0,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000 +[0-9a-f]+ <[^>]*> 0025 ab3c div zero,a1,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768 +[0-9a-f]+ <[^>]*> 0024 ab3c div zero,a0,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768 +[0-9a-f]+ <[^>]*> 0025 ab3c div zero,a1,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1 +[0-9a-f]+ <[^>]*> 0024 ab3c div zero,a0,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1 +[0-9a-f]+ <[^>]*> 0025 ab3c div zero,a1,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1 +[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> 0024 ab3c div zero,a0,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 41a1 0001 lui at,0x1 +[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> 0025 ab3c div zero,a1,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 00a4 bb3c divu zero,a0,a1 +[0-9a-f]+ <[^>]*> 0005 703c teq a1,zero,0x7 +[0-9a-f]+ <[^>]*> 00a4 bb3c divu zero,a0,a1 +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 0006 703c teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00c5 bb3c divu zero,a1,a2 +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 0c84 move a0,a0 +[0-9a-f]+ <[^>]*> 0006 703c teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00c5 ab3c div zero,a1,a2 +[0-9a-f]+ <[^>]*> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b426 fffe bne a2,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_2 +[0-9a-f]+ <[^>]*> 41a1 8000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 0025 603c teq a1,at,0x6 +[0-9a-f]+ <\.L\^_2> 4604 mfhi a0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 0025 bb3c divu zero,a1,at +[0-9a-f]+ <[^>]*> 4604 mfhi a0 + \.\.\. diff --git a/gas/testsuite/gas/mips/micromips@div64-trap.d b/gas/testsuite/gas/mips/micromips@div64-trap.d new file mode 100644 index 0000000..e4e5e68 --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@div64-trap.d @@ -0,0 +1,29 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS 64-bit div with traps +#source: div64.s + +# Test the div macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 0006 703c teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 58c5 ab3c ddiv zero,a1,a2 +[0-9a-f]+ <[^>]*> 3020 ffff li at,-1 +[0-9a-f]+ <[^>]*> b426 fffe bne a2,at,[0-9a-f]+ <[^>]*> + [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^_0 +[0-9a-f]+ <[^>]*> 3020 0001 li at,1 +[0-9a-f]+ <[^>]*> 5821 f808 dsll32 at,at,0x1f +[0-9a-f]+ <[^>]*> 0025 603c teq a1,at,0x6 +[0-9a-f]+ <\.L\^_0> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 3020 0002 li at,2 +[0-9a-f]+ <[^>]*> 5825 bb3c ddivu zero,a1,at +[0-9a-f]+ <[^>]*> 4644 mflo a0 +[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000 +[0-9a-f]+ <[^>]*> 5825 ab3c ddiv zero,a1,at +[0-9a-f]+ <[^>]*> 4604 mfhi a0 +[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768 +[0-9a-f]+ <[^>]*> 5825 bb3c ddivu zero,a1,at +[0-9a-f]+ <[^>]*> 4604 mfhi a0 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index f809d9d..7ba674a 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -727,8 +727,12 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "div" [mips_arch_list_matching mips1 \ !mips32r6] + run_dump_test_arches "div-trap" [mips_arch_list_matching mips1 \ + !mips32r6] run_dump_test_arches "div64" [mips_arch_list_matching mips3 !r5900 \ !mips64r6] + run_dump_test_arches "div64-trap" [mips_arch_list_matching mips3 !r5900 \ + !mips64r6] if { !$addr32 && $has_newabi } { run_dump_test_arches "dli" [mips_arch_list_matching mips3] diff --git a/gas/testsuite/gas/mips/mips1@div-trap.d b/gas/testsuite/gas/mips/mips1@div-trap.d new file mode 100644 index 0000000..bca128d --- /dev/null +++ b/gas/testsuite/gas/mips/mips1@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses +#name: MIPS div with traps +#source: div.s +#dump: mips1@div.d diff --git a/gas/testsuite/gas/mips/mips2@div-trap.d b/gas/testsuite/gas/mips/mips2@div-trap.d new file mode 100644 index 0000000..f5b411c --- /dev/null +++ b/gas/testsuite/gas/mips/mips2@div-trap.d @@ -0,0 +1,98 @@ +#as: -32 -trap +#objdump: -drz --prefix-addresses --show-raw-insn +#name: MIPS div with traps +#source: div.s + +# Test the div macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 0085001a div zero,a0,a1 +[0-9a-f]+ <[^>]*> 00a001f4 teq a1,zero,0x7 +[0-9a-f]+ <[^>]*> 0085001a div zero,a0,a1 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14a10002 bne a1,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 008101b4 teq a0,at,0x6 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00c001f4 teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00a6001a div zero,a1,a2 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14c10002 bne a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 00a101b4 teq a1,at,0x6 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00802025 move a0,a0 +[0-9a-f]+ <[^>]*> 00a02025 move a0,a1 +[0-9a-f]+ <[^>]*> 00042022 neg a0,a0 +[0-9a-f]+ <[^>]*> 00052022 neg a0,a1 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 34018000 li at,0x8000 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 34018000 li at,0x8000 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 24018000 li at,-32768 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 24018000 li at,-32768 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1 +[0-9a-f]+ <[^>]*> 3421a5a5 ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> 0081001a div zero,a0,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 3c010001 lui at,0x1 +[0-9a-f]+ <[^>]*> 3421a5a5 ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> 00a1001a div zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0085001b divu zero,a0,a1 +[0-9a-f]+ <[^>]*> 00a001f4 teq a1,zero,0x7 +[0-9a-f]+ <[^>]*> 0085001b divu zero,a0,a1 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00c001f4 teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00a6001b divu zero,a1,a2 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 00802025 move a0,a0 +[0-9a-f]+ <[^>]*> 00c001f4 teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00a6001a div zero,a1,a2 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14c10002 bne a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 3c018000 lui at,0x8000 +[0-9a-f]+ <[^>]*> 00a101b4 teq a1,at,0x6 +[0-9a-f]+ <[^>]*> 00002010 mfhi a0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00a1001b divu zero,a1,at +[0-9a-f]+ <[^>]*> 00002010 mfhi a0 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00000000 nop diff --git a/gas/testsuite/gas/mips/mips3@div-trap.d b/gas/testsuite/gas/mips/mips3@div-trap.d new file mode 100644 index 0000000..9086b22 --- /dev/null +++ b/gas/testsuite/gas/mips/mips3@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -drz --prefix-addresses --show-raw-insn +#name: MIPS div with traps +#source: div.s +#dump: mips2@div-trap.d diff --git a/gas/testsuite/gas/mips/mips3@div64-trap.d b/gas/testsuite/gas/mips/mips3@div64-trap.d new file mode 100644 index 0000000..568fbd4 --- /dev/null +++ b/gas/testsuite/gas/mips/mips3@div64-trap.d @@ -0,0 +1,31 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS 64-bit div with traps +#source: div64.s + +# Test the div macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 00c001f4 teq a2,zero,0x7 +[0-9a-f]+ <[^>]*> 00a6001e ddiv zero,a1,a2 +[0-9a-f]+ <[^>]*> 2401ffff li at,-1 +[0-9a-f]+ <[^>]*> 14c10003 bne a2,at,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 24010001 li at,1 +[0-9a-f]+ <[^>]*> 00010ffc dsll32 at,at,0x1f +[0-9a-f]+ <[^>]*> 00a101b4 teq a1,at,0x6 +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 24010002 li at,2 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00a1001f ddivu zero,a1,at +[0-9a-f]+ <[^>]*> 00002012 mflo a0 +[0-9a-f]+ <[^>]*> 34018000 li at,0x8000 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00a1001e ddiv zero,a1,at +[0-9a-f]+ <[^>]*> 00002010 mfhi a0 +[0-9a-f]+ <[^>]*> 24018000 li at,-32768 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00a1001f ddivu zero,a1,at +[0-9a-f]+ <[^>]*> 00002010 mfhi a0 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips4@div-trap.d b/gas/testsuite/gas/mips/mips4@div-trap.d new file mode 100644 index 0000000..9086b22 --- /dev/null +++ b/gas/testsuite/gas/mips/mips4@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -drz --prefix-addresses --show-raw-insn +#name: MIPS div with traps +#source: div.s +#dump: mips2@div-trap.d diff --git a/gas/testsuite/gas/mips/mips4@div64-trap.d b/gas/testsuite/gas/mips/mips4@div64-trap.d new file mode 100644 index 0000000..ad9bada --- /dev/null +++ b/gas/testsuite/gas/mips/mips4@div64-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS 64-bit div with traps +#source: div64.s +#dump: mips3@div64-trap.d diff --git a/gas/testsuite/gas/mips/mips5@div-trap.d b/gas/testsuite/gas/mips/mips5@div-trap.d new file mode 100644 index 0000000..9086b22 --- /dev/null +++ b/gas/testsuite/gas/mips/mips5@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -drz --prefix-addresses --show-raw-insn +#name: MIPS div with traps +#source: div.s +#dump: mips2@div-trap.d diff --git a/gas/testsuite/gas/mips/mips5@div64-trap.d b/gas/testsuite/gas/mips/mips5@div64-trap.d new file mode 100644 index 0000000..ad9bada --- /dev/null +++ b/gas/testsuite/gas/mips/mips5@div64-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS 64-bit div with traps +#source: div64.s +#dump: mips3@div64-trap.d diff --git a/gas/testsuite/gas/mips/r3000@div-trap.d b/gas/testsuite/gas/mips/r3000@div-trap.d new file mode 100644 index 0000000..bca128d --- /dev/null +++ b/gas/testsuite/gas/mips/r3000@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses +#name: MIPS div with traps +#source: div.s +#dump: mips1@div.d diff --git a/gas/testsuite/gas/mips/r3900@div-trap.d b/gas/testsuite/gas/mips/r3900@div-trap.d new file mode 100644 index 0000000..bca128d --- /dev/null +++ b/gas/testsuite/gas/mips/r3900@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses +#name: MIPS div with traps +#source: div.s +#dump: mips1@div.d diff --git a/gas/testsuite/gas/mips/r4000@div-trap.d b/gas/testsuite/gas/mips/r4000@div-trap.d new file mode 100644 index 0000000..9086b22 --- /dev/null +++ b/gas/testsuite/gas/mips/r4000@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -drz --prefix-addresses --show-raw-insn +#name: MIPS div with traps +#source: div.s +#dump: mips2@div-trap.d diff --git a/gas/testsuite/gas/mips/r4000@div64-trap.d b/gas/testsuite/gas/mips/r4000@div64-trap.d new file mode 100644 index 0000000..ad9bada --- /dev/null +++ b/gas/testsuite/gas/mips/r4000@div64-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS 64-bit div with traps +#source: div64.s +#dump: mips3@div64-trap.d diff --git a/gas/testsuite/gas/mips/vr5400@div-trap.d b/gas/testsuite/gas/mips/vr5400@div-trap.d new file mode 100644 index 0000000..9086b22 --- /dev/null +++ b/gas/testsuite/gas/mips/vr5400@div-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -drz --prefix-addresses --show-raw-insn +#name: MIPS div with traps +#source: div.s +#dump: mips2@div-trap.d diff --git a/gas/testsuite/gas/mips/vr5400@div64-trap.d b/gas/testsuite/gas/mips/vr5400@div64-trap.d new file mode 100644 index 0000000..ad9bada --- /dev/null +++ b/gas/testsuite/gas/mips/vr5400@div64-trap.d @@ -0,0 +1,5 @@ +#as: -32 -trap +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS 64-bit div with traps +#source: div64.s +#dump: mips3@div64-trap.d |