opcode/

2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * mips-dis.c (mips_arch_choices): Add Octeon+.
        * mips-opc.c (IOCT): Include Octeon+.
        (IOCTP): New macro.
        (mips_builtin_opcodes): Add "saa" and "saad".
bfd/
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * archures.c (bfd_mach_mips_octeonp): New macro.
        * bfd-in2.h: Regenerate.
        * bfd/cpu-mips.c (I_mipsocteonp): New enum value.
        (arch_info_struct): Add bfd_mach_mips_octeonp.
        * elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
        (mips_mach_extensions): Add bfd_mach_mips_octeonp.
include/opcodes/
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
        (INSN_OCTEONP): New macro.
        (CPU_OCTEONP): New macro.
        (OPCODE_IS_MEMBER): Add Octeon+.
        (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
gas/
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * config/tc-mips.c (CPU_IS_OCTEON): New macro function.
        (CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
        (NO_ISA_COP): Likewise.
        (macro) <ld_st>: Add support when off0 is true.
        Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
        (mips_cpu_info_table): Add octeon+.
        * doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
gas/testsuite/
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * gas/mips/mips.exp: Add octeon+ for an architecture.
        Run octeon-saa-saad test.
        (run_dump_test_arch): For Octeon architectures, also try octeon@.
        * gas/mips/octeon-pref.d: Remove -march=octeon from command line.
        * gas/mips/octeon.d: Likewise.
        * gas/mips/octeon-saa-saad.d: New file.
        * gas/mips/octeon-saa-saad.s: New file

9 files changed, 170 insertions, 15 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d8cf381..eee35de 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2011-11-29  Andrew Pinski  <apinski@cavium.com>
+
+	* config/tc-mips.c (CPU_IS_OCTEON): New macro function.
+	(CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
+	(NO_ISA_COP): Likewise.
+	(macro) <ld_st>: Add support when off0 is true.
+	Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
+	(mips_cpu_info_table): Add octeon+.
+	* doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
+
 2011-11-25  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
 	* config/tc-arm.c (do_t_mov_cmp): Allow MOV lowreg, lowreg when no CPU
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 34d2df7..2a57393 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -497,13 +497,16 @@ static int mips_32bitmode = 0;
 /* True if CPU has a ror instruction.  */
 #define CPU_HAS_ROR(CPU)	CPU_HAS_DROR (CPU)
 
+/* True if CPU is in the Octeon family */
+#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP)
+
 /* True if CPU has seq/sne and seqi/snei instructions.  */
-#define CPU_HAS_SEQ(CPU)	((CPU) == CPU_OCTEON)
+#define CPU_HAS_SEQ(CPU)	(CPU_IS_OCTEON (CPU))
 
 /* True if CPU does not implement the all the coprocessor insns.  For these
    CPUs only those COP insns are accepted that are explicitly marked to be
    available on the CPU.  ISA membership for COP insns is ignored.  */
-#define NO_ISA_COP(CPU)		((CPU) == CPU_OCTEON)
+#define NO_ISA_COP(CPU)		(CPU_IS_OCTEON (CPU))
 
 /* True if mflo and mfhi can be immediately followed by instructions
    which write to the HI and LO registers.
@@ -6261,6 +6264,7 @@ macro (struct mips_cl_insn *ip)
   int ust = 0;
   int lp = 0;
   int ab = 0;
+  int off0 = 0;
   int off;
   offsetT maxnum;
   bfd_reloc_code_real_type r;
@@ -8295,20 +8299,29 @@ macro (struct mips_cl_insn *ip)
 			     tempreg, tempreg, breg);
 	      breg = tempreg;
 	    }
-	  if (!off12)
+	  if (off0)
+	    {
+	      if (offset_expr.X_add_number == 0)
+		tempreg = breg;
+	      else
+		macro_build (&offset_expr, ADDRESS_ADDI_INSN,
+			     "t,r,j", tempreg, breg, BFD_RELOC_LO16);
+	      macro_build (NULL, s, fmt, treg, tempreg);
+	    }
+	  else if (!off12)
 	    macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
 	  else
 	    macro_build (NULL, s, fmt,
 			 treg, (unsigned long) offset_expr.X_add_number, breg);
 	}
-      else if (off12)
+      else if (off12 || off0)
 	{
-	  /* A 12-bit offset field is too narrow to be used for a low-part
-	     relocation, so load the whole address into the auxillary
-	     register.  In the case of "A(b)" addresses, we first load
-	     absolute address "A" into the register and then add base
-	     register "b".  In the case of "o(b)" addresses, we simply
-	     need to add 16-bit offset "o" to base register "b", and
+	  /* A 12-bit or 0-bit offset field is too narrow to be used
+	     for a low-part relocation, so load the whole address into
+	     the auxillary register.  In the case of "A(b)" addresses,
+	     we first load absolute address "A" into the register and
+	     then add base register "b".  In the case of "o(b)" addresses,
+	     we simply need to add 16-bit offset "o" to base register "b", and
 	     offset_reloc already contains the relocations associated
 	     with "o".  */
 	  if (ab)
@@ -8323,8 +8336,11 @@ macro (struct mips_cl_insn *ip)
 			 tempreg, breg, -1,
 			 offset_reloc[0], offset_reloc[1], offset_reloc[2]);
 	  expr1.X_add_number = 0;
-	  macro_build (NULL, s, fmt,
-		       treg, (unsigned long) expr1.X_add_number, tempreg);
+	  if (off0)
+	    macro_build (NULL, s, fmt, treg, tempreg);
+	  else
+	    macro_build (NULL, s, fmt,
+		         treg, (unsigned long) expr1.X_add_number, tempreg);
 	}
       else if (mips_pic == NO_PIC)
 	{
@@ -9118,6 +9134,22 @@ macro (struct mips_cl_insn *ip)
 	}
       break;
 
+	
+    case M_SAA_AB:
+      ab = 1;
+    case M_SAA_OB:
+      s = "saa";
+      off0 = 1;
+      fmt = "t,(b)";
+      goto ld_st;
+    case M_SAAD_AB:
+      ab = 1;
+    case M_SAAD_OB:
+      s = "saad";
+      off0 = 1;
+      fmt = "t,(b)";
+      goto ld_st;
+
    /* New code added to support COPZ instructions.
       This code builds table entries out of the macros in mip_opcodes.
       R4000 uses interlocks to handle coproc delays.
@@ -19042,6 +19074,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
 
   /* Cavium Networks Octeon CPU core */
   { "octeon",	      0,      ISA_MIPS64R2,   CPU_OCTEON },
+  { "octeon+",	      0,      ISA_MIPS64R2,   CPU_OCTEONP },
 
   /* RMI Xlr */
   { "xlr",	      0,      ISA_MIPS64,     CPU_XLR },
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 22c7c38..ddfcbd9 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -323,6 +323,7 @@ loongson2e,
 loongson2f,
 loongson3a,
 octeon,
+octeon+,
 xlr
 @end quotation
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 054eee3..6d0688b 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2011-11-29  Andrew Pinski  <apinski@cavium.com>
+
+	* gas/mips/mips.exp: Add octeon+ for an architecture.
+	Run octeon-saa-saad test.
+	(run_dump_test_arch): For Octeon architectures, also try octeon@.
+	* gas/mips/octeon-pref.d: Remove -march=octeon from command line.
+	* gas/mips/octeon.d: Likewise.
+	* gas/mips/octeon-saa-saad.d: New file.
+	* gas/mips/octeon-saa-saad.s: New file
+
 2011-11-25  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
 	* gas/arm/mov-highregs-any.d: New testcase.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 5d91aef..047c038 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -308,7 +308,13 @@ proc run_dump_test_arch { name arch } {
 
     set format [expr { $elf ? "elf" : $ecoff ? "ecoff" : "aout" }]
     set proparch [lindex [mips_arch_properties $arch 0] 0]
-    foreach prefix [list ${proparch}@${format}@ ${proparch}@ ${format}@] {
+    set prefixes [list ${proparch}@${format}@ ${proparch}@ ]
+    if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } {
+      lappend prefixes octeon@
+      lappend prefixes octeon@${format}@
+    }
+    lappend prefixes ${format}@
+    foreach prefix ${prefixes} {
 	set archname ${prefix}${name}
 	if { [file exists "$srcdir/$subdir/${archname}.d"] } {
 	    set name $archname
@@ -412,6 +418,9 @@ mips_arch_create sb1 	64	mips64	{ mips3d } \
 mips_arch_create octeon 64	mips64r2 {} \
 			{ -march=octeon -mtune=octeon } { -mmips:octeon } \
 			{ mips64octeon*-*-* }
+mips_arch_create octeonp 64	octeon {} \
+			{ -march=octeon+ -mtune=octeon+ } { -mmips:octeon+ } \
+			{ }
 mips_arch_create xlr 	64	mips64	{} \
 			{ -march=xlr -mtune=xlr } { -mmips:xlr }
 
@@ -981,6 +990,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "loongson-3a-3"
 
     run_dump_test_arches "octeon"	[mips_arch_list_matching octeon]
+    run_dump_test_arches "octeon-saa-saad" [mips_arch_list_matching octeonp]
     run_list_test_arches "octeon-ill" "" \
 					[mips_arch_list_matching octeon]
     run_dump_test_arches "octeon-pref"	[mips_arch_list_matching octeon]
diff --git a/gas/testsuite/gas/mips/octeon-pref.d b/gas/testsuite/gas/mips/octeon-pref.d
index 6dcb184..0b536d6 100644
--- a/gas/testsuite/gas/mips/octeon-pref.d
+++ b/gas/testsuite/gas/mips/octeon-pref.d
@@ -1,4 +1,4 @@
-#as: -march=octeon -64 -mfix-cn63xxp1
+#as: -64 -mfix-cn63xxp1
 #objdump: -M reg-names=numeric -dr
 #name: MIPS octeon-pref mfix-cn63xxp1
 
diff --git a/gas/testsuite/gas/mips/octeon-saa-saad.d b/gas/testsuite/gas/mips/octeon-saa-saad.d
new file mode 100644
index 0000000..e5dff8e
--- /dev/null
+++ b/gas/testsuite/gas/mips/octeon-saa-saad.d
@@ -0,0 +1,58 @@
+#objdump: -d -r --show-raw-insn
+#name: MIPS-OCTEON octeon_saa_saad
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <foo>:
+.*:	70450018 	saa	a1,\(v0\)
+.*:	70860019 	saad	a2,\(a0\)
+.*:	00000000 	nop
+.*:	70450018 	saa	a1,\(v0\)
+.*:	70860019 	saad	a2,\(a0\)
+.*:	00000000 	nop
+.*:	3c010000 	lui	at,0x0
+			18: R_MIPS_HI16	.text
+.*:	24210000 	addiu	at,at,0
+			1c: R_MIPS_LO16	.text
+.*:	70250018 	saa	a1,\(at\)
+.*:	3c010000 	lui	at,0x0
+			24: R_MIPS_HI16	.text
+.*:	24210000 	addiu	at,at,0
+			28: R_MIPS_LO16	.text
+.*:	70220019 	saad	v0,\(at\)
+.*:	00000000 	nop
+.*:	3c011234 	lui	at,0x1234
+.*:	24215678 	addiu	at,at,22136
+.*:	70240018 	saa	a0,\(at\)
+.*:	3c011234 	lui	at,0x1234
+.*:	24215678 	addiu	at,at,22136
+.*:	70240019 	saad	a0,\(at\)
+.*:	00000000 	nop
+.*:	24811234 	addiu	at,a0,4660
+.*:	70250018 	saa	a1,\(at\)
+.*:	2401003c 	li	at,60
+.*:	70260019 	saad	a2,\(at\)
+.*:	00000000 	nop
+.*:	3c010012 	lui	at,0x12
+.*:	00240821 	addu	at,at,a0
+.*:	24213456 	addiu	at,at,13398
+.*:	70250018 	saa	a1,\(at\)
+.*:	24c11234 	addiu	at,a2,4660
+.*:	70260018 	saa	a2,\(at\)
+.*:	00000000 	nop
+.*:	24a15678 	addiu	at,a1,22136
+.*:	70240019 	saad	a0,\(at\)
+.*:	3c010056 	lui	at,0x56
+.*:	00250821 	addu	at,at,a1
+.*:	24217891 	addiu	at,at,30865
+.*:	70250019 	saad	a1,\(at\)
+.*:	00000000 	nop
+.*:	24a10000 	addiu	at,a1,0
+			9c: R_MIPS_LO16	.text
+.*:	70240018 	saa	a0,\(at\)
+.*:	24a10000 	addiu	at,a1,0
+			a4: R_MIPS_LO16	.text
+.*:	70240019 	saad	a0,\(at\)
+.*:	00000000 	nop
diff --git a/gas/testsuite/gas/mips/octeon-saa-saad.s b/gas/testsuite/gas/mips/octeon-saa-saad.s
new file mode 100644
index 0000000..22d1a07
--- /dev/null
+++ b/gas/testsuite/gas/mips/octeon-saa-saad.s
@@ -0,0 +1,33 @@
+	.text
+foo:
+	saa $5,($2)
+	saad $6,($4)
+	nop
+
+	saa $5,0($2)
+	saad $6,0($4)
+	nop
+
+	saa $5, foo
+	saad $2, foo
+	nop
+
+	saa $4, 0x12345678
+	saad $4, 0x12345678
+	nop
+
+	saa $5, 0x1234($4)
+	saad $6, 60($0)
+	nop
+
+	saa $5, 0x123456($4)
+	saa $6, 0x1234($6)
+	nop
+
+	saad $4, 0x5678($5)
+	saad $5, 0x567891($5)
+	nop	
+
+	saa $4, %lo(foo)($5)
+	saad $4, %lo(foo)($5)
+	nop
diff --git a/gas/testsuite/gas/mips/octeon.d b/gas/testsuite/gas/mips/octeon.d
index 79b4001..a0e15d8 100644
--- a/gas/testsuite/gas/mips/octeon.d
+++ b/gas/testsuite/gas/mips/octeon.d
@@ -1,4 +1,4 @@
-#as: -march=octeon -64
+#as: -64
 #objdump: -M reg-names=numeric -dr
 #name: MIPS octeon instructions