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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2024-06-06 15:59:52 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-06 16:10:51 +0800 |
| commit | d9c14a8744b01b0d3d03a661c732a4d4d5740fbc (patch) | |
| tree | 104016466320290c6444f5b089e737449cf23f7d /gas | |
| parent | af38c6367ff0c6af1639b389eb34cf9983c30ff5 (diff) | |
| download | binutils-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.zip binutils-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.tar.gz binutils-d9c14a8744b01b0d3d03a661c732a4d4d5740fbc.tar.bz2 | |
RISC-V: Add support for Zvfbfmin extension
This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>
Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.
For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvfbfmin.d: New test.
* testsuite/gas/riscv/zvfbfmin.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
(MASK_VFNCVTBF16_F_F_W): Ditto.
(MATCH_VFWCVTBF16_F_F_V): Ditto.
(MASK_VFWCVTBF16_F_F_V): Ditto.
(DECLARE_INSN): New declarations for Zvfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add
INSN_CLASS_ZVFBFMIN
opcodes/ChangeLog:
* riscv-opc.c: Add Zvfbfmin instructions.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/NEWS | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/march-help.l | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvfbfmin.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/zvfbfmin.s | 7 |
4 files changed, 22 insertions, 0 deletions
@@ -23,6 +23,8 @@ * Add support for RISC-V Zfbfmin extension with version 1.0. +* Add support for RISC-V Zvfbfmin extension with version 1.0. + * The base register operand in D(X,B) and D(L,B) may be explicitly omitted in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) D(X,%r0), D(L,0), and D(L,%r0). diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 57c73b3..38c70e2 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -58,6 +58,7 @@ All available -march extensions for RISC-V: zve64d 1.0 zvbb 1.0 zvbc 1.0 + zvfbfmin 1.0 zvfh 1.0 zvfhmin 1.0 zvkb 1.0 diff --git a/gas/testsuite/gas/riscv/zvfbfmin.d b/gas/testsuite/gas/riscv/zvfbfmin.d new file mode 100644 index 0000000..ce97381 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin.d @@ -0,0 +1,12 @@ +#as: -march=rv64iv_zvfbfmin +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+4a8e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+488e9257[ ]+vfncvtbf16.f.f.w[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48869257[ ]+vfwcvtbf16.f.f.v[ ]+v4,v8,v0.t diff --git a/gas/testsuite/gas/riscv/zvfbfmin.s b/gas/testsuite/gas/riscv/zvfbfmin.s new file mode 100644 index 0000000..9a4493d --- /dev/null +++ b/gas/testsuite/gas/riscv/zvfbfmin.s @@ -0,0 +1,7 @@ +target: + # vfncvtbf16.f.f.w + vfncvtbf16.f.f.w v4, v8 + vfncvtbf16.f.f.w v4, v8, v0.t + # vfwcvtbf16.f.f.v + vfwcvtbf16.f.f.v v4, v8 + vfwcvtbf16.f.f.v v4, v8, v0.t |