bfd/:

2005-02-15  Nigel Stephens  <nigel@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* elf32-mips.c (elf_mips16_howto_table_rel): New array for MIPS16
	reloc howtos.  Add R_MIPS16_HI16 and R_MIPS16_LO16 relocs and
	R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
	(elf_mips16_jump_howto): Move into elf_mips16_howto_table_rel.
	(elf_mips16_gprel_howto): Likewise.  Redefine src_mask and
	dst_mask.
	(mips16_gprel_reloc): Remove bit shuffling; call
	_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
	and _bfd_mips16_elf_reloc_shuffle() instead.
	(mips16_reloc_map): New reloc map for MIPS16 relocs.
	(bfd_elf32_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
	relocs.
	(mips_elf32_rtype_to_howto): Fetch MIPS16 howtos from
	elf_mips16_howto_table_rel.
	* elf64-mips.c (mips16_elf64_howto_table_rel): New array for
	MIPS16 REL reloc howtos.  Add R_MIPS16_HI16 and R_MIPS16_LO16
	relocs and R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
	(elf_mips16_jump_howto): Move into mips16_elf64_howto_table_rel.
	(elf_mips16_gprel_howto): Likewise.  Redefine src_mask and
	dst_mask.
	(mips16_elf64_howto_table_rela): New array for MIPS16 RELA
	reloc howtos.  Add R_MIPS16_26, R_MIPS16_GPREL, R_MIPS16_HI16 and
	R_MIPS16_LO16 relocs and R_MIPS16_GOT16 and R_MIPS16_CALL16
	placeholders.
	(mips16_gprel_reloc): Remove bit shuffling; call
	_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
	and _bfd_mips16_elf_reloc_shuffle() instead.
	(mips16_reloc_map): New reloc map for MIPS16 relocs.
	(bfd_elf64_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
	relocs.
	(mips_elf64_rtype_to_howto): Fetch MIPS16 howtos from
	mips16_elf64_howto_table_rela or mips16_elf64_howto_table_rel.
	* elfn32-mips.c (elf_mips16_howto_table_rel): New array for MIPS16
	REL reloc howtos.  Add R_MIPS16_HI16 and R_MIPS16_LO16 relocs and
	R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
	(elf_mips16_jump_howto): Move into elf_mips16_howto_table_rel.
	(elf_mips16_gprel_howto): Likewise.  Redefine src_mask and
	dst_mask.
	(mips16_gprel_reloc): Remove bit shuffling; call
	_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
	and _bfd_mips16_elf_reloc_shuffle() instead.
	(mips16_reloc_map): New reloc map for MIPS16 relocs.
	(bfd_elf32_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
	relocs.
	(mips_elf_n32_rtype_to_howto): Fetch MIPS16 howtos from
	elf_mips16_howto_table_rela or elf_mips16_howto_table_rel.
	* elfxx-mips.c (_bfd_mips16_elf_reloc_unshuffle): New function to
	handle bit shuffling for MIPS16 relocs.
	(_bfd_mips16_elf_reloc_shuffle): Likewise.
	(_bfd_mips_elf_lo16_reloc): Use _bfd_mips16_elf_reloc_unshuffle()
	and _bfd_mips16_elf_reloc_shuffle().
	(_bfd_mips_elf_generic_reloc): Likewise.
	(mips_elf_calculate_relocation): Likewise.  Handle R_MIPS16_HI16
	and R_MIPS16_LO16.
	(mips_elf_obtain_contents): Remove bit shuffling.
	(mips_elf_perform_relocation): Likewise; call
	_bfd_mips16_elf_reloc_unshuffle() and _bfd_mips16_elf_reloc_shuffle()
	instead.
	(_bfd_mips_elf_relocate_section): Likewise.  Handle R_MIPS16_HI16
	and R_MIPS16_LO16.
	* elfxx-mips.h (_bfd_mips16_elf_reloc_unshuffle): Declare.
	(_bfd_mips16_elf_reloc_shuffle): Likewise.
	* reloc.c (BFD_RELOC_MIPS16_HI16): New reloc.
	(BFD_RELOC_MIPS16_HI16_S): Likewise.
	(BFD_RELOC_MIPS16_LO16): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

gas/:
2005-02-15  Nigel Stephens  <nigel@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* config/tc-mips.c (reloc_needs_lo_p): Handle
	BFD_RELOC_MIPS16_HI16_S.
	(fixup_has_matching_lo_p): Handle BFD_RELOC_MIPS16_LO16.
	(append_insn): Add BFD_RELOC_MIPS16_GPREL, BFD_RELOC_MIPS16_HI16_S
	and BFD_RELOC_MIPS16_LO16 to relocs to suppress overflow
	complaints on.
	(mips16_ip): Resolve BFD_RELOC_MIPS16_HI16_S,
	BFD_RELOC_MIPS16_HI16 and BFD_RELOC_MIPS16_LO16 for constants.
	Call my_getSmallExpression() to parse percent operators.
	(percent_op_match, mips_percent_op): Separate definitions.
	(mips16_percent_op): Define percent operators for the MIPS16 mode.
	(parse_relocation): Handle the MIPS16 mode using
	mips16_percent_op.
	(md_apply_fix3): Handle BFD_RELOC_MIPS16_HI16,
	BFD_RELOC_MIPS16_HI16_S and BFD_RELOC_MIPS16_LO16.

gas/testsuite/:
2005-02-15  Nigel Stephens  <nigel@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* gas/mips/mips16-hilo.d: New test for the R_MIPS16_HI16 and
	R_MIPS16_LO16 relocs.
	* gas/mips/mips16-hilo-n32.d: Likewise, for the n32 ABI.
	* gas/mips/mips16-hilo.s: Source for the new tests.
	* gas/mips/mips.exp: Run the new tests.

include/:
2005-02-15  Nigel Stephens  <nigel@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* elf/mips.h (R_MIPS16_GOT16): New reloc code.
	(R_MIPS16_CALL16): Likewise.
	(R_MIPS16_HI16): Likewise.
	(R_MIPS16_LO16): Likewise.
	(R_MIPS16_min): New fake reloc code.
	(R_MIPS16_max): Likewise.

ld/testsuite/:
2005-02-15  Nigel Stephens  <nigel@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* ld-mips-elf/mips16-hilo.d: New test for the R_MIPS16_HI16 and
	R_MIPS16_LO16 relocs.
	* ld-mips-elf/mips16-hilo-n32.d: Likewise, for the n32 ABI.
	* ld-mips-elf/mips16-hilo.s: Auxiliary source for the new tests.
	* ld-mips-elf/mips-elf.exp: Run the new tests.

7 files changed, 1517 insertions, 32 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index fe8e26d..6296d47 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,22 @@
+2005-02-15  Nigel Stephens  <nigel@mips.com>
+            Maciej W. Rozycki  <macro@mips.com>
+
+	* config/tc-mips.c (reloc_needs_lo_p): Handle
+	BFD_RELOC_MIPS16_HI16_S.
+	(fixup_has_matching_lo_p): Handle BFD_RELOC_MIPS16_LO16.
+	(append_insn): Add BFD_RELOC_MIPS16_GPREL, BFD_RELOC_MIPS16_HI16_S
+	and BFD_RELOC_MIPS16_LO16 to relocs to suppress overflow
+	complaints on.
+	(mips16_ip): Resolve BFD_RELOC_MIPS16_HI16_S,
+	BFD_RELOC_MIPS16_HI16 and BFD_RELOC_MIPS16_LO16 for constants.
+	Call my_getSmallExpression() to parse percent operators.
+	(percent_op_match, mips_percent_op): Separate definitions.
+	(mips16_percent_op): Define percent operators for the MIPS16 mode.
+	(parse_relocation): Handle the MIPS16 mode using
+	mips16_percent_op.
+	(md_apply_fix3): Handle BFD_RELOC_MIPS16_HI16,
+	BFD_RELOC_MIPS16_HI16_S and BFD_RELOC_MIPS16_LO16.
+
 2005-02-15  Jan Beulich  <jbeulich@novell.com>
 
 	* config/tc-ia64.c (md_apply_fix3): Call ia64_gen_real_reloc_type
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index d3cf055..834ecd9 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1407,7 +1407,8 @@ reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
 {
   return (HAVE_IN_PLACE_ADDENDS
 	  && (reloc == BFD_RELOC_HI16_S
-	      || reloc == BFD_RELOC_MIPS_GOT16));
+	      || reloc == BFD_RELOC_MIPS_GOT16
+	      || reloc == BFD_RELOC_MIPS16_HI16_S));
 }
 
 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
@@ -1417,7 +1418,8 @@ static inline bfd_boolean
 fixup_has_matching_lo_p (fixS *fixp)
 {
   return (fixp->fx_next != NULL
-	  && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
+	  && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16
+	     || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16)
 	  && fixp->fx_addsy == fixp->fx_next->fx_addsy
 	  && fixp->fx_offset == fixp->fx_next->fx_offset);
 }
@@ -2194,7 +2196,10 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 		  || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
 		  || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
 		  || reloc_type[0] == BFD_RELOC_MIPS_REL16
-		  || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
+		  || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
+		  || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
+		  || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
+		  || reloc_type[0] == BFD_RELOC_MIPS16_LO16))
 	    fixp[0]->fx_no_overflow = 1;
 
 	  if (mips_relax.sequence)
@@ -9097,6 +9102,7 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
   unsigned int regno;
   unsigned int lastregno = 0;
   char *s_reset;
+  size_t i;
 
   insn_error = NULL;
 
@@ -9183,8 +9189,34 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		      && *imm_reloc > BFD_RELOC_UNUSED
 		      && insn->pinfo != INSN_MACRO)
 		    {
+		      valueT tmp;
+
+		      switch (*offset_reloc)
+			{
+			  case BFD_RELOC_MIPS16_HI16_S:
+			    tmp = (imm_expr.X_add_number + 0x8000) >> 16;
+			    break;
+
+			  case BFD_RELOC_MIPS16_HI16:
+			    tmp = imm_expr.X_add_number >> 16;
+			    break;
+
+			  case BFD_RELOC_MIPS16_LO16:
+			    tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
+				  - 0x8000;
+			    break;
+
+			  case BFD_RELOC_UNUSED:
+			    tmp = imm_expr.X_add_number;
+			    break;
+
+			  default:
+			    internalError ();
+			}
+		      *offset_reloc = BFD_RELOC_UNUSED;
+
 		      mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
-				    imm_expr.X_add_number, TRUE, mips16_small,
+				    tmp, TRUE, mips16_small,
 				    mips16_ext, &ip->insn_opcode,
 				    &ip->use_extend, &ip->extend);
 		      imm_expr.X_op = O_absent;
@@ -9395,47 +9427,43 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		}
 	      break;
 
-	    case '<':
-	    case '>':
-	    case '[':
-	    case ']':
-	    case '4':
 	    case '5':
 	    case 'H':
 	    case 'W':
 	    case 'D':
 	    case 'j':
-	    case '8':
 	    case 'V':
 	    case 'C':
 	    case 'U':
 	    case 'k':
 	    case 'K':
-	      if (s[0] == '%'
-		  && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
+	      i = my_getSmallExpression (&imm_expr, imm_reloc, s);
+	      if (i > 0)
 		{
-		  /* This is %gprel(SYMBOL).  We need to read SYMBOL,
-                     and generate the appropriate reloc.  If the text
-                     inside %gprel is not a symbol name with an
-                     optional offset, then we generate a normal reloc
-                     and will probably fail later.  */
-		  my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
-		  if (imm_expr.X_op == O_symbol)
+		  if (imm_expr.X_op != O_constant)
 		    {
 		      mips16_ext = TRUE;
-		      *imm_reloc = BFD_RELOC_MIPS16_GPREL;
-		      s = expr_end;
 		      ip->use_extend = TRUE;
 		      ip->extend = 0;
-		      continue;
 		    }
+		  else
+		    {
+		      /* We need to relax this instruction.  */
+		      *offset_reloc = *imm_reloc;
+		      *imm_reloc = (int) BFD_RELOC_UNUSED + c;
+		    }
+		  s = expr_end;
+		  continue;
 		}
-	      else
-		{
-		  /* Just pick up a normal expression.  */
-		  my_getExpression (&imm_expr, s);
-		}
-
+	      *imm_reloc = BFD_RELOC_UNUSED;
+	      /* Fall through.  */
+	    case '<':
+	    case '>':
+	    case '[':
+	    case ']':
+	    case '4':
+	    case '8':
+	      my_getExpression (&imm_expr, s);
 	      if (imm_expr.X_op == O_register)
 		{
 		  /* What we thought was an expression turned out to
@@ -9797,11 +9825,13 @@ mips16_immed (char *file, unsigned int line, int type, offsetT val,
     }
 }
 
-static const struct percent_op_match
+struct percent_op_match
 {
   const char *str;
   bfd_reloc_code_real_type reloc;
-} percent_op[] =
+};
+
+static const struct percent_op_match mips_percent_op[] =
 {
   {"%lo", BFD_RELOC_LO16},
 #ifdef OBJ_ELF
@@ -9823,6 +9853,13 @@ static const struct percent_op_match
   {"%hi", BFD_RELOC_HI16_S}
 };
 
+static const struct percent_op_match mips16_percent_op[] =
+{
+  {"%lo", BFD_RELOC_MIPS16_LO16},
+  {"%gprel", BFD_RELOC_MIPS16_GPREL},
+  {"%hi", BFD_RELOC_MIPS16_HI16_S}
+};
+
 
 /* Return true if *STR points to a relocation operator.  When returning true,
    move *STR over the operator and store its relocation code in *RELOC.
@@ -9831,9 +9868,21 @@ static const struct percent_op_match
 static bfd_boolean
 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
 {
-  size_t i;
+  const struct percent_op_match *percent_op;
+  size_t limit, i;
+
+  if (mips_opts.mips16)
+    {
+      percent_op = mips16_percent_op;
+      limit = ARRAY_SIZE (mips16_percent_op);
+    }
+  else
+    {
+      percent_op = mips_percent_op;
+      limit = ARRAY_SIZE (mips_percent_op);
+    }
 
-  for (i = 0; i < ARRAY_SIZE (percent_op); i++)
+  for (i = 0; i < limit; i++)
     if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
       {
 	*str += strlen (percent_op[i].str);
@@ -11000,6 +11049,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_MIPS_CALL_HI16:
     case BFD_RELOC_MIPS_CALL_LO16:
     case BFD_RELOC_MIPS16_GPREL:
+    case BFD_RELOC_MIPS16_HI16:
+    case BFD_RELOC_MIPS16_HI16_S:
       assert (! fixP->fx_pcrel);
       /* Nothing needed to do. The value comes from the reloc entry */
       break;
@@ -11051,6 +11102,7 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       break;
 
     case BFD_RELOC_LO16:
+    case BFD_RELOC_MIPS16_LO16:
       /* FIXME: Now that embedded-PIC is gone, some of this code/comment
 	 may be safe to remove, but if so it's not obvious.  */
       /* When handling an embedded PIC switch statement, we can wind
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index e1c1781..777b195 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2005-02-15  Nigel Stephens  <nigel@mips.com>
+            Maciej W. Rozycki  <macro@mips.com>
+
+	* gas/mips/mips16-hilo.d: New test for the R_MIPS16_HI16 and
+	R_MIPS16_LO16 relocs.
+	* gas/mips/mips16-hilo-n32.d: Likewise, for the n32 ABI.
+	* gas/mips/mips16-hilo.s: Source for the new tests.
+	* gas/mips/mips.exp: Run the new tests.
+
 2005-02-15  Jan Beulich  <jbeulich@novell.com>
 
 	* gas/ia64/pcrel.[ds]: New.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 4c1e308..42e0c4b 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -529,6 +529,11 @@ if { [istarget mips*-*-*] } then {
 	# Check jalx handling
 	run_dump_test "mips16-jalx"
 	run_dump_test "mips-jalx"
+	# Check MIPS16 HI16/LO16 relocations
+	run_dump_test "mips16-hilo"
+	if $has_newabi {
+	    run_dump_test "mips16-hilo-n32"
+	}
     }
     run_list_test "mips-no-jalx" "-32"
     run_dump_test "delay"
diff --git a/gas/testsuite/gas/mips/mips16-hilo-n32.d b/gas/testsuite/gas/mips/mips16-hilo-n32.d
new file mode 100644
index 0000000..2e3c8a1
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-hilo-n32.d
@@ -0,0 +1,527 @@
+#objdump: -dr
+#name: MIPS16 lui/addi n32
+#as: -mips16 -mabi=n32 -march=mips64
+#source: mips16-hilo.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+0+0000 <stuff>:
+   0:	6c00      	li	a0,0
+   2:	f400 3480 	sll	a0,16
+   6:	4c00      	addiu	a0,0
+   8:	f000 6c00 	li	a0,0
+			8: R_MIPS16_HI16	\.data
+   c:	f400 3480 	sll	a0,16
+  10:	f000 4c00 	addiu	a0,0
+			10: R_MIPS16_LO16	\.data
+  14:	f000 6c00 	li	a0,0
+			14: R_MIPS16_HI16	\.data\+0x4
+  18:	f400 3480 	sll	a0,16
+  1c:	f000 4c00 	addiu	a0,0
+			1c: R_MIPS16_LO16	\.data\+0x4
+  20:	f000 6c00 	li	a0,0
+			20: R_MIPS16_HI16	big_external_data_label
+  24:	f400 3480 	sll	a0,16
+  28:	f000 4c00 	addiu	a0,0
+			28: R_MIPS16_LO16	big_external_data_label
+  2c:	f000 6c00 	li	a0,0
+			2c: R_MIPS16_HI16	small_external_data_label
+  30:	f400 3480 	sll	a0,16
+  34:	f000 4c00 	addiu	a0,0
+			34: R_MIPS16_LO16	small_external_data_label
+  38:	f000 6c00 	li	a0,0
+			38: R_MIPS16_HI16	big_external_common
+  3c:	f400 3480 	sll	a0,16
+  40:	f000 4c00 	addiu	a0,0
+			40: R_MIPS16_LO16	big_external_common
+  44:	f000 6c00 	li	a0,0
+			44: R_MIPS16_HI16	small_external_common
+  48:	f400 3480 	sll	a0,16
+  4c:	f000 4c00 	addiu	a0,0
+			4c: R_MIPS16_LO16	small_external_common
+  50:	f000 6c00 	li	a0,0
+			50: R_MIPS16_HI16	\.bss
+  54:	f400 3480 	sll	a0,16
+  58:	f000 4c00 	addiu	a0,0
+			58: R_MIPS16_LO16	\.bss
+  5c:	f000 6c00 	li	a0,0
+			5c: R_MIPS16_HI16	\.sbss
+  60:	f400 3480 	sll	a0,16
+  64:	f000 4c00 	addiu	a0,0
+			64: R_MIPS16_LO16	\.sbss
+  68:	6c00      	li	a0,0
+  6a:	f400 3480 	sll	a0,16
+  6e:	4c01      	addiu	a0,1
+  70:	f000 6c00 	li	a0,0
+			70: R_MIPS16_HI16	\.data\+0x1
+  74:	f400 3480 	sll	a0,16
+  78:	f000 4c00 	addiu	a0,0
+			78: R_MIPS16_LO16	\.data\+0x1
+  7c:	f000 6c00 	li	a0,0
+			7c: R_MIPS16_HI16	\.data\+0x5
+  80:	f400 3480 	sll	a0,16
+  84:	f000 4c00 	addiu	a0,0
+			84: R_MIPS16_LO16	\.data\+0x5
+  88:	f000 6c00 	li	a0,0
+			88: R_MIPS16_HI16	big_external_data_label\+0x1
+  8c:	f400 3480 	sll	a0,16
+  90:	f000 4c00 	addiu	a0,0
+			90: R_MIPS16_LO16	big_external_data_label\+0x1
+  94:	f000 6c00 	li	a0,0
+			94: R_MIPS16_HI16	small_external_data_label\+0x1
+  98:	f400 3480 	sll	a0,16
+  9c:	f000 4c00 	addiu	a0,0
+			9c: R_MIPS16_LO16	small_external_data_label\+0x1
+  a0:	f000 6c00 	li	a0,0
+			a0: R_MIPS16_HI16	big_external_common\+0x1
+  a4:	f400 3480 	sll	a0,16
+  a8:	f000 4c00 	addiu	a0,0
+			a8: R_MIPS16_LO16	big_external_common\+0x1
+  ac:	f000 6c00 	li	a0,0
+			ac: R_MIPS16_HI16	small_external_common\+0x1
+  b0:	f400 3480 	sll	a0,16
+  b4:	f000 4c00 	addiu	a0,0
+			b4: R_MIPS16_LO16	small_external_common\+0x1
+  b8:	f000 6c00 	li	a0,0
+			b8: R_MIPS16_HI16	\.bss\+0x1
+  bc:	f400 3480 	sll	a0,16
+  c0:	f000 4c00 	addiu	a0,0
+			c0: R_MIPS16_LO16	\.bss\+0x1
+  c4:	f000 6c00 	li	a0,0
+			c4: R_MIPS16_HI16	\.sbss\+0x1
+  c8:	f400 3480 	sll	a0,16
+  cc:	f000 4c00 	addiu	a0,0
+			cc: R_MIPS16_LO16	\.sbss\+0x1
+  d0:	6c01      	li	a0,1
+  d2:	f400 3480 	sll	a0,16
+  d6:	f010 4c00 	addiu	a0,-32768
+  da:	f000 6c00 	li	a0,0
+			da: R_MIPS16_HI16	\.data\+0x8000
+  de:	f400 3480 	sll	a0,16
+  e2:	f000 4c00 	addiu	a0,0
+			e2: R_MIPS16_LO16	\.data\+0x8000
+  e6:	f000 6c00 	li	a0,0
+			e6: R_MIPS16_HI16	\.data\+0x8004
+  ea:	f400 3480 	sll	a0,16
+  ee:	f000 4c00 	addiu	a0,0
+			ee: R_MIPS16_LO16	\.data\+0x8004
+  f2:	f000 6c00 	li	a0,0
+			f2: R_MIPS16_HI16	big_external_data_label\+0x8000
+  f6:	f400 3480 	sll	a0,16
+  fa:	f000 4c00 	addiu	a0,0
+			fa: R_MIPS16_LO16	big_external_data_label\+0x8000
+  fe:	f000 6c00 	li	a0,0
+			fe: R_MIPS16_HI16	small_external_data_label\+0x8000
+ 102:	f400 3480 	sll	a0,16
+ 106:	f000 4c00 	addiu	a0,0
+			106: R_MIPS16_LO16	small_external_data_label\+0x8000
+ 10a:	f000 6c00 	li	a0,0
+			10a: R_MIPS16_HI16	big_external_common\+0x8000
+ 10e:	f400 3480 	sll	a0,16
+ 112:	f000 4c00 	addiu	a0,0
+			112: R_MIPS16_LO16	big_external_common\+0x8000
+ 116:	f000 6c00 	li	a0,0
+			116: R_MIPS16_HI16	small_external_common\+0x8000
+ 11a:	f400 3480 	sll	a0,16
+ 11e:	f000 4c00 	addiu	a0,0
+			11e: R_MIPS16_LO16	small_external_common\+0x8000
+ 122:	f000 6c00 	li	a0,0
+			122: R_MIPS16_HI16	\.bss\+0x8000
+ 126:	f400 3480 	sll	a0,16
+ 12a:	f000 4c00 	addiu	a0,0
+			12a: R_MIPS16_LO16	\.bss\+0x8000
+ 12e:	f000 6c00 	li	a0,0
+			12e: R_MIPS16_HI16	\.sbss\+0x8000
+ 132:	f400 3480 	sll	a0,16
+ 136:	f000 4c00 	addiu	a0,0
+			136: R_MIPS16_LO16	\.sbss\+0x8000
+ 13a:	6c00      	li	a0,0
+ 13c:	f400 3480 	sll	a0,16
+ 140:	f010 4c00 	addiu	a0,-32768
+ 144:	f000 6c00 	li	a0,0
+			144: R_MIPS16_HI16	\.data\+0xffff8000
+ 148:	f400 3480 	sll	a0,16
+ 14c:	f000 4c00 	addiu	a0,0
+			14c: R_MIPS16_LO16	\.data\+0xffff8000
+ 150:	f000 6c00 	li	a0,0
+			150: R_MIPS16_HI16	\.data\+0xffff8004
+ 154:	f400 3480 	sll	a0,16
+ 158:	f000 4c00 	addiu	a0,0
+			158: R_MIPS16_LO16	\.data\+0xffff8004
+ 15c:	f000 6c00 	li	a0,0
+			15c: R_MIPS16_HI16	big_external_data_label\+0xffff8000
+ 160:	f400 3480 	sll	a0,16
+ 164:	f000 4c00 	addiu	a0,0
+			164: R_MIPS16_LO16	big_external_data_label\+0xffff8000
+ 168:	f000 6c00 	li	a0,0
+			168: R_MIPS16_HI16	small_external_data_label\+0xffff8000
+ 16c:	f400 3480 	sll	a0,16
+ 170:	f000 4c00 	addiu	a0,0
+			170: R_MIPS16_LO16	small_external_data_label\+0xffff8000
+ 174:	f000 6c00 	li	a0,0
+			174: R_MIPS16_HI16	big_external_common\+0xffff8000
+ 178:	f400 3480 	sll	a0,16
+ 17c:	f000 4c00 	addiu	a0,0
+			17c: R_MIPS16_LO16	big_external_common\+0xffff8000
+ 180:	f000 6c00 	li	a0,0
+			180: R_MIPS16_HI16	small_external_common\+0xffff8000
+ 184:	f400 3480 	sll	a0,16
+ 188:	f000 4c00 	addiu	a0,0
+			188: R_MIPS16_LO16	small_external_common\+0xffff8000
+ 18c:	f000 6c00 	li	a0,0
+			18c: R_MIPS16_HI16	\.bss\+0xffff8000
+ 190:	f400 3480 	sll	a0,16
+ 194:	f000 4c00 	addiu	a0,0
+			194: R_MIPS16_LO16	\.bss\+0xffff8000
+ 198:	f000 6c00 	li	a0,0
+			198: R_MIPS16_HI16	\.sbss\+0xffff8000
+ 19c:	f400 3480 	sll	a0,16
+ 1a0:	f000 4c00 	addiu	a0,0
+			1a0: R_MIPS16_LO16	\.sbss\+0xffff8000
+ 1a4:	6c01      	li	a0,1
+ 1a6:	f400 3480 	sll	a0,16
+ 1aa:	4c00      	addiu	a0,0
+ 1ac:	f000 6c00 	li	a0,0
+			1ac: R_MIPS16_HI16	\.data\+0x10000
+ 1b0:	f400 3480 	sll	a0,16
+ 1b4:	f000 4c00 	addiu	a0,0
+			1b4: R_MIPS16_LO16	\.data\+0x10000
+ 1b8:	f000 6c00 	li	a0,0
+			1b8: R_MIPS16_HI16	\.data\+0x10004
+ 1bc:	f400 3480 	sll	a0,16
+ 1c0:	f000 4c00 	addiu	a0,0
+			1c0: R_MIPS16_LO16	\.data\+0x10004
+ 1c4:	f000 6c00 	li	a0,0
+			1c4: R_MIPS16_HI16	big_external_data_label\+0x10000
+ 1c8:	f400 3480 	sll	a0,16
+ 1cc:	f000 4c00 	addiu	a0,0
+			1cc: R_MIPS16_LO16	big_external_data_label\+0x10000
+ 1d0:	f000 6c00 	li	a0,0
+			1d0: R_MIPS16_HI16	small_external_data_label\+0x10000
+ 1d4:	f400 3480 	sll	a0,16
+ 1d8:	f000 4c00 	addiu	a0,0
+			1d8: R_MIPS16_LO16	small_external_data_label\+0x10000
+ 1dc:	f000 6c00 	li	a0,0
+			1dc: R_MIPS16_HI16	big_external_common\+0x10000
+ 1e0:	f400 3480 	sll	a0,16
+ 1e4:	f000 4c00 	addiu	a0,0
+			1e4: R_MIPS16_LO16	big_external_common\+0x10000
+ 1e8:	f000 6c00 	li	a0,0
+			1e8: R_MIPS16_HI16	small_external_common\+0x10000
+ 1ec:	f400 3480 	sll	a0,16
+ 1f0:	f000 4c00 	addiu	a0,0
+			1f0: R_MIPS16_LO16	small_external_common\+0x10000
+ 1f4:	f000 6c00 	li	a0,0
+			1f4: R_MIPS16_HI16	\.bss\+0x10000
+ 1f8:	f400 3480 	sll	a0,16
+ 1fc:	f000 4c00 	addiu	a0,0
+			1fc: R_MIPS16_LO16	\.bss\+0x10000
+ 200:	f000 6c00 	li	a0,0
+			200: R_MIPS16_HI16	\.sbss\+0x10000
+ 204:	f400 3480 	sll	a0,16
+ 208:	f000 4c00 	addiu	a0,0
+			208: R_MIPS16_LO16	\.sbss\+0x10000
+ 20c:	6c02      	li	a0,2
+ 20e:	f400 3480 	sll	a0,16
+ 212:	f5b4 4c05 	addiu	a0,-23131
+ 216:	f000 6c00 	li	a0,0
+			216: R_MIPS16_HI16	\.data\+0x1a5a5
+ 21a:	f400 3480 	sll	a0,16
+ 21e:	f000 4c00 	addiu	a0,0
+			21e: R_MIPS16_LO16	\.data\+0x1a5a5
+ 222:	f000 6c00 	li	a0,0
+			222: R_MIPS16_HI16	\.data\+0x1a5a9
+ 226:	f400 3480 	sll	a0,16
+ 22a:	f000 4c00 	addiu	a0,0
+			22a: R_MIPS16_LO16	\.data\+0x1a5a9
+ 22e:	f000 6c00 	li	a0,0
+			22e: R_MIPS16_HI16	big_external_data_label\+0x1a5a5
+ 232:	f400 3480 	sll	a0,16
+ 236:	f000 4c00 	addiu	a0,0
+			236: R_MIPS16_LO16	big_external_data_label\+0x1a5a5
+ 23a:	f000 6c00 	li	a0,0
+			23a: R_MIPS16_HI16	small_external_data_label\+0x1a5a5
+ 23e:	f400 3480 	sll	a0,16
+ 242:	f000 4c00 	addiu	a0,0
+			242: R_MIPS16_LO16	small_external_data_label\+0x1a5a5
+ 246:	f000 6c00 	li	a0,0
+			246: R_MIPS16_HI16	big_external_common\+0x1a5a5
+ 24a:	f400 3480 	sll	a0,16
+ 24e:	f000 4c00 	addiu	a0,0
+			24e: R_MIPS16_LO16	big_external_common\+0x1a5a5
+ 252:	f000 6c00 	li	a0,0
+			252: R_MIPS16_HI16	small_external_common\+0x1a5a5
+ 256:	f400 3480 	sll	a0,16
+ 25a:	f000 4c00 	addiu	a0,0
+			25a: R_MIPS16_LO16	small_external_common\+0x1a5a5
+ 25e:	f000 6c00 	li	a0,0
+			25e: R_MIPS16_HI16	\.bss\+0x1a5a5
+ 262:	f400 3480 	sll	a0,16
+ 266:	f000 4c00 	addiu	a0,0
+			266: R_MIPS16_LO16	\.bss\+0x1a5a5
+ 26a:	f000 6c00 	li	a0,0
+			26a: R_MIPS16_HI16	\.sbss\+0x1a5a5
+ 26e:	f400 3480 	sll	a0,16
+ 272:	f000 4c00 	addiu	a0,0
+			272: R_MIPS16_LO16	\.sbss\+0x1a5a5
+ 276:	6d00      	li	a1,0
+ 278:	f400 35a0 	sll	a1,16
+ 27c:	9d80      	lw	a0,0\(a1\)
+ 27e:	f000 6d00 	li	a1,0
+			27e: R_MIPS16_HI16	\.data
+ 282:	f400 35a0 	sll	a1,16
+ 286:	f000 9d80 	lw	a0,0\(a1\)
+			286: R_MIPS16_HI16	\.data
+ 28a:	f000 6d00 	li	a1,0
+			28a: R_MIPS16_HI16	\.data\+0x4
+ 28e:	f400 35a0 	sll	a1,16
+ 292:	f000 9d80 	lw	a0,0\(a1\)
+			292: R_MIPS16_HI16	\.data\+0x4
+ 296:	f000 6d00 	li	a1,0
+			296: R_MIPS16_HI16	big_external_data_label
+ 29a:	f400 35a0 	sll	a1,16
+ 29e:	f000 9d80 	lw	a0,0\(a1\)
+			29e: R_MIPS16_LO16	big_external_data_label
+ 2a2:	f000 6d00 	li	a1,0
+			2a2: R_MIPS16_HI16	small_external_data_label
+ 2a6:	f400 35a0 	sll	a1,16
+ 2aa:	f000 9d80 	lw	a0,0\(a1\)
+			2aa: R_MIPS16_LO16	small_external_data_label
+ 2ae:	f000 6d00 	li	a1,0
+			2ae: R_MIPS16_HI16	big_external_common
+ 2b2:	f400 35a0 	sll	a1,16
+ 2b6:	f000 9d80 	lw	a0,0\(a1\)
+			2b6: R_MIPS16_LO16	big_external_common
+ 2ba:	f000 6d00 	li	a1,0
+			2ba: R_MIPS16_HI16	small_external_common
+ 2be:	f400 35a0 	sll	a1,16
+ 2c2:	f000 9d80 	lw	a0,0\(a1\)
+			2c2: R_MIPS16_LO16	small_external_common
+ 2c6:	f000 6d00 	li	a1,0
+			2c6: R_MIPS16_HI16	\.bss
+ 2ca:	f400 35a0 	sll	a1,16
+ 2ce:	f000 9d80 	lw	a0,0\(a1\)
+			2ce: R_MIPS16_LO16	\.bss
+ 2d2:	f000 6d00 	li	a1,0
+			2d2: R_MIPS16_HI16	\.sbss
+ 2d6:	f400 35a0 	sll	a1,16
+ 2da:	f000 9d80 	lw	a0,0\(a1\)
+			2da: R_MIPS16_LO16	\.sbss
+ 2de:	6d00      	li	a1,0
+ 2e0:	f400 35a0 	sll	a1,16
+ 2e4:	f000 9d81 	lw	a0,1\(a1\)
+ 2e8:	f000 6d00 	li	a1,0
+			2e8: R_MIPS16_HI16	\.data\+0x1
+ 2ec:	f400 35a0 	sll	a1,16
+ 2f0:	f000 9d80 	lw	a0,0\(a1\)
+			2f0: R_MIPS16_LO16	\.data\+0x1
+ 2f4:	f000 6d00 	li	a1,0
+			2f4: R_MIPS16_HI16	\.data\+0x5
+ 2f8:	f400 35a0 	sll	a1,16
+ 2fc:	f000 9d80 	lw	a0,0\(a1\)
+			2fc: R_MIPS16_LO16	\.data\+0x5
+ 300:	f000 6d00 	li	a1,0
+			300: R_MIPS16_HI16	big_external_data_label\+0x1
+ 304:	f400 35a0 	sll	a1,16
+ 308:	f000 9d80 	lw	a0,0\(a1\)
+			308: R_MIPS16_LO16	big_external_data_label\+0x1
+ 30c:	f000 6d00 	li	a1,0
+			30c: R_MIPS16_HI16	small_external_data_label\+0x1
+ 310:	f400 35a0 	sll	a1,16
+ 314:	f000 9d80 	lw	a0,0\(a1\)
+			314: R_MIPS16_LO16	small_external_data_label\+0x1
+ 318:	f000 6d00 	li	a1,0
+			318: R_MIPS16_HI16	big_external_common\+0x1
+ 31c:	f400 35a0 	sll	a1,16
+ 320:	f000 9d80 	lw	a0,0\(a1\)
+			320: R_MIPS16_LO16	big_external_common\+0x1
+ 324:	f000 6d00 	li	a1,0
+			324: R_MIPS16_HI16	small_external_common\+0x1
+ 328:	f400 35a0 	sll	a1,16
+ 32c:	f000 9d80 	lw	a0,0\(a1\)
+			32c: R_MIPS16_LO16	small_external_common\+0x1
+ 330:	f000 6d00 	li	a1,0
+			330: R_MIPS16_HI16	\.bss\+0x1
+ 334:	f400 35a0 	sll	a1,16
+ 338:	f000 9d80 	lw	a0,0\(a1\)
+			338: R_MIPS16_LO16	\.bss\+0x1
+ 33c:	f000 6d00 	li	a1,0
+			33c: R_MIPS16_HI16	\.sbss\+0x1
+ 340:	f400 35a0 	sll	a1,16
+ 344:	f000 9d80 	lw	a0,0\(a1\)
+			344: R_MIPS16_LO16	\.sbss\+0x1
+ 348:	6d01      	li	a1,1
+ 34a:	f400 35a0 	sll	a1,16
+ 34e:	f010 9d80 	lw	a0,-32768\(a1\)
+ 352:	f000 6d00 	li	a1,0
+			352: R_MIPS16_HI16	\.data\+0x8000
+ 356:	f400 35a0 	sll	a1,16
+ 35a:	f000 9d80 	lw	a0,0\(a1\)
+			35a: R_MIPS16_LO16	\.data\+0x8000
+ 35e:	f000 6d00 	li	a1,0
+			35e: R_MIPS16_HI16	\.data\+0x8004
+ 362:	f400 35a0 	sll	a1,16
+ 366:	f000 9d80 	lw	a0,0\(a1\)
+			366: R_MIPS16_LO16	\.data\+0x8004
+ 36a:	f000 6d00 	li	a1,0
+			36a: R_MIPS16_HI16	big_external_data_label\+0x8000
+ 36e:	f400 35a0 	sll	a1,16
+ 372:	f000 9d80 	lw	a0,0\(a1\)
+			372: R_MIPS16_LO16	big_external_data_label\+0x8000
+ 376:	f000 6d00 	li	a1,0
+			376: R_MIPS16_HI16	small_external_data_label\+0x8000
+ 37a:	f400 35a0 	sll	a1,16
+ 37e:	f000 9d80 	lw	a0,0\(a1\)
+			37e: R_MIPS16_LO16	small_external_data_label\+0x8000
+ 382:	f000 6d00 	li	a1,0
+			382: R_MIPS16_HI16	big_external_common\+0x8000
+ 386:	f400 35a0 	sll	a1,16
+ 38a:	f000 9d80 	lw	a0,0\(a1\)
+			38a: R_MIPS16_LO16	big_external_common\+0x8000
+ 38e:	f000 6d00 	li	a1,0
+			38e: R_MIPS16_HI16	small_external_common\+0x8000
+ 392:	f400 35a0 	sll	a1,16
+ 396:	f000 9d80 	lw	a0,0\(a1\)
+			396: R_MIPS16_LO16	small_external_common\+0x8000
+ 39a:	f000 6d00 	li	a1,0
+			39a: R_MIPS16_HI16	\.bss\+0x8000
+ 39e:	f400 35a0 	sll	a1,16
+ 3a2:	f000 9d80 	lw	a0,0\(a1\)
+			3a2: R_MIPS16_LO16	\.bss\+0x8000
+ 3a6:	f000 6d00 	li	a1,0
+			3a6: R_MIPS16_HI16	\.sbss\+0x8000
+ 3aa:	f400 35a0 	sll	a1,16
+ 3ae:	f000 9d80 	lw	a0,0\(a1\)
+			3ae: R_MIPS16_LO16	\.sbss\+0x8000
+ 3b2:	6d00      	li	a1,0
+ 3b4:	f400 35a0 	sll	a1,16
+ 3b8:	f010 9d80 	lw	a0,-32768\(a1\)
+ 3bc:	f000 6d00 	li	a1,0
+			3bc: R_MIPS16_HI16	\.data\+0xffff8000
+ 3c0:	f400 35a0 	sll	a1,16
+ 3c4:	f000 9d80 	lw	a0,0\(a1\)
+			3c4: R_MIPS16_LO16	\.data\+0xffff8000
+ 3c8:	f000 6d00 	li	a1,0
+			3c8: R_MIPS16_HI16	\.data\+0xffff8004
+ 3cc:	f400 35a0 	sll	a1,16
+ 3d0:	f000 9d80 	lw	a0,0\(a1\)
+			3d0: R_MIPS16_LO16	\.data\+0xffff8004
+ 3d4:	f000 6d00 	li	a1,0
+			3d4: R_MIPS16_HI16	big_external_data_label\+0xffff8000
+ 3d8:	f400 35a0 	sll	a1,16
+ 3dc:	f000 9d80 	lw	a0,0\(a1\)
+			3dc: R_MIPS16_LO16	big_external_data_label\+0xffff8000
+ 3e0:	f000 6d00 	li	a1,0
+			3e0: R_MIPS16_HI16	small_external_data_label\+0xffff8000
+ 3e4:	f400 35a0 	sll	a1,16
+ 3e8:	f000 9d80 	lw	a0,0\(a1\)
+			3e8: R_MIPS16_LO16	small_external_data_label\+0xffff8000
+ 3ec:	f000 6d00 	li	a1,0
+			3ec: R_MIPS16_HI16	big_external_common\+0xffff8000
+ 3f0:	f400 35a0 	sll	a1,16
+ 3f4:	f000 9d80 	lw	a0,0\(a1\)
+			3f4: R_MIPS16_LO16	big_external_common\+0xffff8000
+ 3f8:	f000 6d00 	li	a1,0
+			3f8: R_MIPS16_HI16	small_external_common\+0xffff8000
+ 3fc:	f400 35a0 	sll	a1,16
+ 400:	f000 9d80 	lw	a0,0\(a1\)
+			400: R_MIPS16_LO16	small_external_common\+0xffff8000
+ 404:	f000 6d00 	li	a1,0
+			404: R_MIPS16_HI16	\.bss\+0xffff8000
+ 408:	f400 35a0 	sll	a1,16
+ 40c:	f000 9d80 	lw	a0,0\(a1\)
+			40c: R_MIPS16_LO16	\.bss\+0xffff8000
+ 410:	f000 6d00 	li	a1,0
+			410: R_MIPS16_HI16	\.sbss\+0xffff8000
+ 414:	f400 35a0 	sll	a1,16
+ 418:	f000 9d80 	lw	a0,0\(a1\)
+			418: R_MIPS16_LO16	\.sbss\+0xffff8000
+ 41c:	6d01      	li	a1,1
+ 41e:	f400 35a0 	sll	a1,16
+ 422:	9d80      	lw	a0,0\(a1\)
+ 424:	f000 6d00 	li	a1,0
+			424: R_MIPS16_HI16	\.data\+0x10000
+ 428:	f400 35a0 	sll	a1,16
+ 42c:	f000 9d80 	lw	a0,0\(a1\)
+			42c: R_MIPS16_LO16	\.data\+0x10000
+ 430:	f000 6d00 	li	a1,0
+			430: R_MIPS16_HI16	\.data\+0x10004
+ 434:	f400 35a0 	sll	a1,16
+ 438:	f000 9d80 	lw	a0,0\(a1\)
+			438: R_MIPS16_LO16	\.data\+0x10004
+ 43c:	f000 6d00 	li	a1,0
+			43c: R_MIPS16_HI16	big_external_data_label\+0x10000
+ 440:	f400 35a0 	sll	a1,16
+ 444:	f000 9d80 	lw	a0,0\(a1\)
+			444: R_MIPS16_LO16	big_external_data_label\+0x10000
+ 448:	f000 6d00 	li	a1,0
+			448: R_MIPS16_HI16	small_external_data_label\+0x10000
+ 44c:	f400 35a0 	sll	a1,16
+ 450:	f000 9d80 	lw	a0,0\(a1\)
+			450: R_MIPS16_LO16	small_external_data_label\+0x10000
+ 454:	f000 6d00 	li	a1,0
+			454: R_MIPS16_HI16	big_external_common\+0x10000
+ 458:	f400 35a0 	sll	a1,16
+ 45c:	f000 9d80 	lw	a0,0\(a1\)
+			45c: R_MIPS16_LO16	big_external_common\+0x10000
+ 460:	f000 6d00 	li	a1,0
+			460: R_MIPS16_HI16	small_external_common\+0x10000
+ 464:	f400 35a0 	sll	a1,16
+ 468:	f000 9d80 	lw	a0,0\(a1\)
+			468: R_MIPS16_LO16	small_external_common\+0x10000
+ 46c:	f000 6d00 	li	a1,0
+			46c: R_MIPS16_HI16	\.bss\+0x10000
+ 470:	f400 35a0 	sll	a1,16
+ 474:	f000 9d80 	lw	a0,0\(a1\)
+			474: R_MIPS16_LO16	\.bss\+0x10000
+ 478:	f000 6d00 	li	a1,0
+			478: R_MIPS16_HI16	\.sbss\+0x10000
+ 47c:	f400 35a0 	sll	a1,16
+ 480:	f000 9d80 	lw	a0,0\(a1\)
+			480: R_MIPS16_LO16	\.sbss\+0x10000
+ 484:	6d02      	li	a1,2
+ 486:	f400 35a0 	sll	a1,16
+ 48a:	f5b4 9d85 	lw	a0,-23131\(a1\)
+ 48e:	f000 6d00 	li	a1,0
+			48e: R_MIPS16_HI16	\.data\+0x1a5a5
+ 492:	f400 35a0 	sll	a1,16
+ 496:	f000 9d80 	lw	a0,0\(a1\)
+			496: R_MIPS16_LO16	\.data\+0x1a5a5
+ 49a:	f000 6d00 	li	a1,0
+			49a: R_MIPS16_HI16	\.data\+0x1a5a9
+ 49e:	f400 35a0 	sll	a1,16
+ 4a2:	f000 9d80 	lw	a0,0\(a1\)
+			4a2: R_MIPS16_LO16	\.data\+0x1a5a9
+ 4a6:	f000 6d00 	li	a1,0
+			4a6: R_MIPS16_HI16	big_external_data_label\+0x1a5a5
+ 4aa:	f400 35a0 	sll	a1,16
+ 4ae:	f000 9d80 	lw	a0,0\(a1\)
+			4ae: R_MIPS16_LO16	big_external_data_label\+0x1a5a5
+ 4b2:	f000 6d00 	li	a1,0
+			4b2: R_MIPS16_HI16	small_external_data_label\+0x1a5a5
+ 4b6:	f400 35a0 	sll	a1,16
+ 4ba:	f000 9d80 	lw	a0,0\(a1\)
+			4ba: R_MIPS16_LO16	small_external_data_label\+0x1a5a5
+ 4be:	f000 6d00 	li	a1,0
+			4be: R_MIPS16_HI16	big_external_common\+0x1a5a5
+ 4c2:	f400 35a0 	sll	a1,16
+ 4c6:	f000 9d80 	lw	a0,0\(a1\)
+			4c6: R_MIPS16_LO16	big_external_common\+0x1a5a5
+ 4ca:	f000 6d00 	li	a1,0
+			4ca: R_MIPS16_HI16	small_external_common\+0x1a5a5
+ 4ce:	f400 35a0 	sll	a1,16
+ 4d2:	f000 9d80 	lw	a0,0\(a1\)
+			4d2: R_MIPS16_LO16	small_external_common\+0x1a5a5
+ 4d6:	f000 6d00 	li	a1,0
+			4d6: R_MIPS16_HI16	\.bss\+0x1a5a5
+ 4da:	f400 35a0 	sll	a1,16
+ 4de:	f000 9d80 	lw	a0,0\(a1\)
+			4de: R_MIPS16_LO16	\.bss\+0x1a5a5
+ 4e2:	f000 6d00 	li	a1,0
+			4e2: R_MIPS16_HI16	\.sbss\+0x1a5a5
+ 4e6:	f400 35a0 	sll	a1,16
+ 4ea:	f000 9d80 	lw	a0,0\(a1\)
+			4ea: R_MIPS16_LO16	\.sbss\+0x1a5a5
+ 4ee:	6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16-hilo.d b/gas/testsuite/gas/mips/mips16-hilo.d
new file mode 100644
index 0000000..081993a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-hilo.d
@@ -0,0 +1,527 @@
+#objdump: -dr
+#name: MIPS16 lui/addi
+#as: -mips16 -mabi=32
+#source: mips16-hilo.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+0+0000 <stuff>:
+   0:	6c00      	li	a0,0
+   2:	f400 3480 	sll	a0,16
+   6:	4c00      	addiu	a0,0
+   8:	f000 6c00 	li	a0,0
+			8: R_MIPS16_HI16	\.data
+   c:	f400 3480 	sll	a0,16
+  10:	f000 4c00 	addiu	a0,0
+			10: R_MIPS16_LO16	\.data
+  14:	f000 6c00 	li	a0,0
+			14: R_MIPS16_HI16	\.data
+  18:	f400 3480 	sll	a0,16
+  1c:	f000 4c04 	addiu	a0,4
+			1c: R_MIPS16_LO16	\.data
+  20:	f000 6c00 	li	a0,0
+			20: R_MIPS16_HI16	big_external_data_label
+  24:	f400 3480 	sll	a0,16
+  28:	f000 4c00 	addiu	a0,0
+			28: R_MIPS16_LO16	big_external_data_label
+  2c:	f000 6c00 	li	a0,0
+			2c: R_MIPS16_HI16	small_external_data_label
+  30:	f400 3480 	sll	a0,16
+  34:	f000 4c00 	addiu	a0,0
+			34: R_MIPS16_LO16	small_external_data_label
+  38:	f000 6c00 	li	a0,0
+			38: R_MIPS16_HI16	big_external_common
+  3c:	f400 3480 	sll	a0,16
+  40:	f000 4c00 	addiu	a0,0
+			40: R_MIPS16_LO16	big_external_common
+  44:	f000 6c00 	li	a0,0
+			44: R_MIPS16_HI16	small_external_common
+  48:	f400 3480 	sll	a0,16
+  4c:	f000 4c00 	addiu	a0,0
+			4c: R_MIPS16_LO16	small_external_common
+  50:	f000 6c00 	li	a0,0
+			50: R_MIPS16_HI16	\.bss
+  54:	f400 3480 	sll	a0,16
+  58:	f000 4c00 	addiu	a0,0
+			58: R_MIPS16_LO16	\.bss
+  5c:	f000 6c00 	li	a0,0
+			5c: R_MIPS16_HI16	\.sbss
+  60:	f400 3480 	sll	a0,16
+  64:	f000 4c00 	addiu	a0,0
+			64: R_MIPS16_LO16	\.sbss
+  68:	6c00      	li	a0,0
+  6a:	f400 3480 	sll	a0,16
+  6e:	4c01      	addiu	a0,1
+  70:	f000 6c00 	li	a0,0
+			70: R_MIPS16_HI16	\.data
+  74:	f400 3480 	sll	a0,16
+  78:	f000 4c01 	addiu	a0,1
+			78: R_MIPS16_LO16	\.data
+  7c:	f000 6c00 	li	a0,0
+			7c: R_MIPS16_HI16	\.data
+  80:	f400 3480 	sll	a0,16
+  84:	f000 4c05 	addiu	a0,5
+			84: R_MIPS16_LO16	\.data
+  88:	f000 6c00 	li	a0,0
+			88: R_MIPS16_HI16	big_external_data_label
+  8c:	f400 3480 	sll	a0,16
+  90:	f000 4c01 	addiu	a0,1
+			90: R_MIPS16_LO16	big_external_data_label
+  94:	f000 6c00 	li	a0,0
+			94: R_MIPS16_HI16	small_external_data_label
+  98:	f400 3480 	sll	a0,16
+  9c:	f000 4c01 	addiu	a0,1
+			9c: R_MIPS16_LO16	small_external_data_label
+  a0:	f000 6c00 	li	a0,0
+			a0: R_MIPS16_HI16	big_external_common
+  a4:	f400 3480 	sll	a0,16
+  a8:	f000 4c01 	addiu	a0,1
+			a8: R_MIPS16_LO16	big_external_common
+  ac:	f000 6c00 	li	a0,0
+			ac: R_MIPS16_HI16	small_external_common
+  b0:	f400 3480 	sll	a0,16
+  b4:	f000 4c01 	addiu	a0,1
+			b4: R_MIPS16_LO16	small_external_common
+  b8:	f000 6c00 	li	a0,0
+			b8: R_MIPS16_HI16	\.bss
+  bc:	f400 3480 	sll	a0,16
+  c0:	f000 4c01 	addiu	a0,1
+			c0: R_MIPS16_LO16	\.bss
+  c4:	f000 6c00 	li	a0,0
+			c4: R_MIPS16_HI16	\.sbss
+  c8:	f400 3480 	sll	a0,16
+  cc:	f000 4c01 	addiu	a0,1
+			cc: R_MIPS16_LO16	\.sbss
+  d0:	6c01      	li	a0,1
+  d2:	f400 3480 	sll	a0,16
+  d6:	f010 4c00 	addiu	a0,-32768
+  da:	f000 6c01 	li	a0,1
+			da: R_MIPS16_HI16	\.data
+  de:	f400 3480 	sll	a0,16
+  e2:	f010 4c00 	addiu	a0,-32768
+			e2: R_MIPS16_LO16	\.data
+  e6:	f000 6c01 	li	a0,1
+			e6: R_MIPS16_HI16	\.data
+  ea:	f400 3480 	sll	a0,16
+  ee:	f010 4c04 	addiu	a0,-32764
+			ee: R_MIPS16_LO16	\.data
+  f2:	f000 6c01 	li	a0,1
+			f2: R_MIPS16_HI16	big_external_data_label
+  f6:	f400 3480 	sll	a0,16
+  fa:	f010 4c00 	addiu	a0,-32768
+			fa: R_MIPS16_LO16	big_external_data_label
+  fe:	f000 6c01 	li	a0,1
+			fe: R_MIPS16_HI16	small_external_data_label
+ 102:	f400 3480 	sll	a0,16
+ 106:	f010 4c00 	addiu	a0,-32768
+			106: R_MIPS16_LO16	small_external_data_label
+ 10a:	f000 6c01 	li	a0,1
+			10a: R_MIPS16_HI16	big_external_common
+ 10e:	f400 3480 	sll	a0,16
+ 112:	f010 4c00 	addiu	a0,-32768
+			112: R_MIPS16_LO16	big_external_common
+ 116:	f000 6c01 	li	a0,1
+			116: R_MIPS16_HI16	small_external_common
+ 11a:	f400 3480 	sll	a0,16
+ 11e:	f010 4c00 	addiu	a0,-32768
+			11e: R_MIPS16_LO16	small_external_common
+ 122:	f000 6c01 	li	a0,1
+			122: R_MIPS16_HI16	\.bss
+ 126:	f400 3480 	sll	a0,16
+ 12a:	f010 4c00 	addiu	a0,-32768
+			12a: R_MIPS16_LO16	\.bss
+ 12e:	f000 6c01 	li	a0,1
+			12e: R_MIPS16_HI16	\.sbss
+ 132:	f400 3480 	sll	a0,16
+ 136:	f010 4c00 	addiu	a0,-32768
+			136: R_MIPS16_LO16	\.sbss
+ 13a:	6c00      	li	a0,0
+ 13c:	f400 3480 	sll	a0,16
+ 140:	f010 4c00 	addiu	a0,-32768
+ 144:	f000 6c00 	li	a0,0
+			144: R_MIPS16_HI16	\.data
+ 148:	f400 3480 	sll	a0,16
+ 14c:	f010 4c00 	addiu	a0,-32768
+			14c: R_MIPS16_LO16	\.data
+ 150:	f000 6c00 	li	a0,0
+			150: R_MIPS16_HI16	\.data
+ 154:	f400 3480 	sll	a0,16
+ 158:	f010 4c04 	addiu	a0,-32764
+			158: R_MIPS16_LO16	\.data
+ 15c:	f000 6c00 	li	a0,0
+			15c: R_MIPS16_HI16	big_external_data_label
+ 160:	f400 3480 	sll	a0,16
+ 164:	f010 4c00 	addiu	a0,-32768
+			164: R_MIPS16_LO16	big_external_data_label
+ 168:	f000 6c00 	li	a0,0
+			168: R_MIPS16_HI16	small_external_data_label
+ 16c:	f400 3480 	sll	a0,16
+ 170:	f010 4c00 	addiu	a0,-32768
+			170: R_MIPS16_LO16	small_external_data_label
+ 174:	f000 6c00 	li	a0,0
+			174: R_MIPS16_HI16	big_external_common
+ 178:	f400 3480 	sll	a0,16
+ 17c:	f010 4c00 	addiu	a0,-32768
+			17c: R_MIPS16_LO16	big_external_common
+ 180:	f000 6c00 	li	a0,0
+			180: R_MIPS16_HI16	small_external_common
+ 184:	f400 3480 	sll	a0,16
+ 188:	f010 4c00 	addiu	a0,-32768
+			188: R_MIPS16_LO16	small_external_common
+ 18c:	f000 6c00 	li	a0,0
+			18c: R_MIPS16_HI16	\.bss
+ 190:	f400 3480 	sll	a0,16
+ 194:	f010 4c00 	addiu	a0,-32768
+			194: R_MIPS16_LO16	\.bss
+ 198:	f000 6c00 	li	a0,0
+			198: R_MIPS16_HI16	\.sbss
+ 19c:	f400 3480 	sll	a0,16
+ 1a0:	f010 4c00 	addiu	a0,-32768
+			1a0: R_MIPS16_LO16	\.sbss
+ 1a4:	6c01      	li	a0,1
+ 1a6:	f400 3480 	sll	a0,16
+ 1aa:	4c00      	addiu	a0,0
+ 1ac:	f000 6c01 	li	a0,1
+			1ac: R_MIPS16_HI16	\.data
+ 1b0:	f400 3480 	sll	a0,16
+ 1b4:	f000 4c00 	addiu	a0,0
+			1b4: R_MIPS16_LO16	\.data
+ 1b8:	f000 6c01 	li	a0,1
+			1b8: R_MIPS16_HI16	\.data
+ 1bc:	f400 3480 	sll	a0,16
+ 1c0:	f000 4c04 	addiu	a0,4
+			1c0: R_MIPS16_LO16	\.data
+ 1c4:	f000 6c01 	li	a0,1
+			1c4: R_MIPS16_HI16	big_external_data_label
+ 1c8:	f400 3480 	sll	a0,16
+ 1cc:	f000 4c00 	addiu	a0,0
+			1cc: R_MIPS16_LO16	big_external_data_label
+ 1d0:	f000 6c01 	li	a0,1
+			1d0: R_MIPS16_HI16	small_external_data_label
+ 1d4:	f400 3480 	sll	a0,16
+ 1d8:	f000 4c00 	addiu	a0,0
+			1d8: R_MIPS16_LO16	small_external_data_label
+ 1dc:	f000 6c01 	li	a0,1
+			1dc: R_MIPS16_HI16	big_external_common
+ 1e0:	f400 3480 	sll	a0,16
+ 1e4:	f000 4c00 	addiu	a0,0
+			1e4: R_MIPS16_LO16	big_external_common
+ 1e8:	f000 6c01 	li	a0,1
+			1e8: R_MIPS16_HI16	small_external_common
+ 1ec:	f400 3480 	sll	a0,16
+ 1f0:	f000 4c00 	addiu	a0,0
+			1f0: R_MIPS16_LO16	small_external_common
+ 1f4:	f000 6c01 	li	a0,1
+			1f4: R_MIPS16_HI16	\.bss
+ 1f8:	f400 3480 	sll	a0,16
+ 1fc:	f000 4c00 	addiu	a0,0
+			1fc: R_MIPS16_LO16	\.bss
+ 200:	f000 6c01 	li	a0,1
+			200: R_MIPS16_HI16	\.sbss
+ 204:	f400 3480 	sll	a0,16
+ 208:	f000 4c00 	addiu	a0,0
+			208: R_MIPS16_LO16	\.sbss
+ 20c:	6c02      	li	a0,2
+ 20e:	f400 3480 	sll	a0,16
+ 212:	f5b4 4c05 	addiu	a0,-23131
+ 216:	f000 6c02 	li	a0,2
+			216: R_MIPS16_HI16	\.data
+ 21a:	f400 3480 	sll	a0,16
+ 21e:	f5b4 4c05 	addiu	a0,-23131
+			21e: R_MIPS16_LO16	\.data
+ 222:	f000 6c02 	li	a0,2
+			222: R_MIPS16_HI16	\.data
+ 226:	f400 3480 	sll	a0,16
+ 22a:	f5b4 4c09 	addiu	a0,-23127
+			22a: R_MIPS16_LO16	\.data
+ 22e:	f000 6c02 	li	a0,2
+			22e: R_MIPS16_HI16	big_external_data_label
+ 232:	f400 3480 	sll	a0,16
+ 236:	f5b4 4c05 	addiu	a0,-23131
+			236: R_MIPS16_LO16	big_external_data_label
+ 23a:	f000 6c02 	li	a0,2
+			23a: R_MIPS16_HI16	small_external_data_label
+ 23e:	f400 3480 	sll	a0,16
+ 242:	f5b4 4c05 	addiu	a0,-23131
+			242: R_MIPS16_LO16	small_external_data_label
+ 246:	f000 6c02 	li	a0,2
+			246: R_MIPS16_HI16	big_external_common
+ 24a:	f400 3480 	sll	a0,16
+ 24e:	f5b4 4c05 	addiu	a0,-23131
+			24e: R_MIPS16_LO16	big_external_common
+ 252:	f000 6c02 	li	a0,2
+			252: R_MIPS16_HI16	small_external_common
+ 256:	f400 3480 	sll	a0,16
+ 25a:	f5b4 4c05 	addiu	a0,-23131
+			25a: R_MIPS16_LO16	small_external_common
+ 25e:	f000 6c02 	li	a0,2
+			25e: R_MIPS16_HI16	\.bss
+ 262:	f400 3480 	sll	a0,16
+ 266:	f5b4 4c05 	addiu	a0,-23131
+			266: R_MIPS16_LO16	\.bss
+ 26a:	f000 6c02 	li	a0,2
+			26a: R_MIPS16_HI16	\.sbss
+ 26e:	f400 3480 	sll	a0,16
+ 272:	f5b4 4c05 	addiu	a0,-23131
+			272: R_MIPS16_LO16	\.sbss
+ 276:	6d00      	li	a1,0
+ 278:	f400 35a0 	sll	a1,16
+ 27c:	9d80      	lw	a0,0\(a1\)
+ 27e:	f000 6d00 	li	a1,0
+			27e: R_MIPS16_HI16	\.data
+ 282:	f400 35a0 	sll	a1,16
+ 286:	f000 9d80 	lw	a0,0\(a1\)
+			286: R_MIPS16_HI16	\.data
+ 28a:	f000 6d00 	li	a1,0
+			28a: R_MIPS16_HI16	\.data
+ 28e:	f400 35a0 	sll	a1,16
+ 292:	f000 9d80 	lw	a0,0\(a1\)
+			292: R_MIPS16_HI16	\.data
+ 296:	f000 6d00 	li	a1,0
+			296: R_MIPS16_HI16	big_external_data_label
+ 29a:	f400 35a0 	sll	a1,16
+ 29e:	f000 9d80 	lw	a0,0\(a1\)
+			29e: R_MIPS16_LO16	big_external_data_label
+ 2a2:	f000 6d00 	li	a1,0
+			2a2: R_MIPS16_HI16	small_external_data_label
+ 2a6:	f400 35a0 	sll	a1,16
+ 2aa:	f000 9d80 	lw	a0,0\(a1\)
+			2aa: R_MIPS16_LO16	small_external_data_label
+ 2ae:	f000 6d00 	li	a1,0
+			2ae: R_MIPS16_HI16	big_external_common
+ 2b2:	f400 35a0 	sll	a1,16
+ 2b6:	f000 9d80 	lw	a0,0\(a1\)
+			2b6: R_MIPS16_LO16	big_external_common
+ 2ba:	f000 6d00 	li	a1,0
+			2ba: R_MIPS16_HI16	small_external_common
+ 2be:	f400 35a0 	sll	a1,16
+ 2c2:	f000 9d80 	lw	a0,0\(a1\)
+			2c2: R_MIPS16_LO16	small_external_common
+ 2c6:	f000 6d00 	li	a1,0
+			2c6: R_MIPS16_HI16	\.bss
+ 2ca:	f400 35a0 	sll	a1,16
+ 2ce:	f000 9d80 	lw	a0,0\(a1\)
+			2ce: R_MIPS16_LO16	\.bss
+ 2d2:	f000 6d00 	li	a1,0
+			2d2: R_MIPS16_HI16	\.sbss
+ 2d6:	f400 35a0 	sll	a1,16
+ 2da:	f000 9d80 	lw	a0,0\(a1\)
+			2da: R_MIPS16_LO16	\.sbss
+ 2de:	6d00      	li	a1,0
+ 2e0:	f400 35a0 	sll	a1,16
+ 2e4:	f000 9d81 	lw	a0,1\(a1\)
+ 2e8:	f000 6d00 	li	a1,0
+			2e8: R_MIPS16_HI16	\.data
+ 2ec:	f400 35a0 	sll	a1,16
+ 2f0:	f000 9d81 	lw	a0,1\(a1\)
+			2f0: R_MIPS16_LO16	\.data
+ 2f4:	f000 6d00 	li	a1,0
+			2f4: R_MIPS16_HI16	\.data
+ 2f8:	f400 35a0 	sll	a1,16
+ 2fc:	f000 9d85 	lw	a0,5\(a1\)
+			2fc: R_MIPS16_LO16	\.data
+ 300:	f000 6d00 	li	a1,0
+			300: R_MIPS16_HI16	big_external_data_label
+ 304:	f400 35a0 	sll	a1,16
+ 308:	f000 9d81 	lw	a0,1\(a1\)
+			308: R_MIPS16_LO16	big_external_data_label
+ 30c:	f000 6d00 	li	a1,0
+			30c: R_MIPS16_HI16	small_external_data_label
+ 310:	f400 35a0 	sll	a1,16
+ 314:	f000 9d81 	lw	a0,1\(a1\)
+			314: R_MIPS16_LO16	small_external_data_label
+ 318:	f000 6d00 	li	a1,0
+			318: R_MIPS16_HI16	big_external_common
+ 31c:	f400 35a0 	sll	a1,16
+ 320:	f000 9d81 	lw	a0,1\(a1\)
+			320: R_MIPS16_LO16	big_external_common
+ 324:	f000 6d00 	li	a1,0
+			324: R_MIPS16_HI16	small_external_common
+ 328:	f400 35a0 	sll	a1,16
+ 32c:	f000 9d81 	lw	a0,1\(a1\)
+			32c: R_MIPS16_LO16	small_external_common
+ 330:	f000 6d00 	li	a1,0
+			330: R_MIPS16_HI16	\.bss
+ 334:	f400 35a0 	sll	a1,16
+ 338:	f000 9d81 	lw	a0,1\(a1\)
+			338: R_MIPS16_LO16	\.bss
+ 33c:	f000 6d00 	li	a1,0
+			33c: R_MIPS16_HI16	\.sbss
+ 340:	f400 35a0 	sll	a1,16
+ 344:	f000 9d81 	lw	a0,1\(a1\)
+			344: R_MIPS16_LO16	\.sbss
+ 348:	6d01      	li	a1,1
+ 34a:	f400 35a0 	sll	a1,16
+ 34e:	f010 9d80 	lw	a0,-32768\(a1\)
+ 352:	f000 6d01 	li	a1,1
+			352: R_MIPS16_HI16	\.data
+ 356:	f400 35a0 	sll	a1,16
+ 35a:	f010 9d80 	lw	a0,-32768\(a1\)
+			35a: R_MIPS16_LO16	\.data
+ 35e:	f000 6d01 	li	a1,1
+			35e: R_MIPS16_HI16	\.data
+ 362:	f400 35a0 	sll	a1,16
+ 366:	f010 9d84 	lw	a0,-32764\(a1\)
+			366: R_MIPS16_LO16	\.data
+ 36a:	f000 6d01 	li	a1,1
+			36a: R_MIPS16_HI16	big_external_data_label
+ 36e:	f400 35a0 	sll	a1,16
+ 372:	f010 9d80 	lw	a0,-32768\(a1\)
+			372: R_MIPS16_LO16	big_external_data_label
+ 376:	f000 6d01 	li	a1,1
+			376: R_MIPS16_HI16	small_external_data_label
+ 37a:	f400 35a0 	sll	a1,16
+ 37e:	f010 9d80 	lw	a0,-32768\(a1\)
+			37e: R_MIPS16_LO16	small_external_data_label
+ 382:	f000 6d01 	li	a1,1
+			382: R_MIPS16_HI16	big_external_common
+ 386:	f400 35a0 	sll	a1,16
+ 38a:	f010 9d80 	lw	a0,-32768\(a1\)
+			38a: R_MIPS16_LO16	big_external_common
+ 38e:	f000 6d01 	li	a1,1
+			38e: R_MIPS16_HI16	small_external_common
+ 392:	f400 35a0 	sll	a1,16
+ 396:	f010 9d80 	lw	a0,-32768\(a1\)
+			396: R_MIPS16_LO16	small_external_common
+ 39a:	f000 6d01 	li	a1,1
+			39a: R_MIPS16_HI16	\.bss
+ 39e:	f400 35a0 	sll	a1,16
+ 3a2:	f010 9d80 	lw	a0,-32768\(a1\)
+			3a2: R_MIPS16_LO16	\.bss
+ 3a6:	f000 6d01 	li	a1,1
+			3a6: R_MIPS16_HI16	\.sbss
+ 3aa:	f400 35a0 	sll	a1,16
+ 3ae:	f010 9d80 	lw	a0,-32768\(a1\)
+			3ae: R_MIPS16_LO16	\.sbss
+ 3b2:	6d00      	li	a1,0
+ 3b4:	f400 35a0 	sll	a1,16
+ 3b8:	f010 9d80 	lw	a0,-32768\(a1\)
+ 3bc:	f000 6d00 	li	a1,0
+			3bc: R_MIPS16_HI16	\.data
+ 3c0:	f400 35a0 	sll	a1,16
+ 3c4:	f010 9d80 	lw	a0,-32768\(a1\)
+			3c4: R_MIPS16_LO16	\.data
+ 3c8:	f000 6d00 	li	a1,0
+			3c8: R_MIPS16_HI16	\.data
+ 3cc:	f400 35a0 	sll	a1,16
+ 3d0:	f010 9d84 	lw	a0,-32764\(a1\)
+			3d0: R_MIPS16_LO16	\.data
+ 3d4:	f000 6d00 	li	a1,0
+			3d4: R_MIPS16_HI16	big_external_data_label
+ 3d8:	f400 35a0 	sll	a1,16
+ 3dc:	f010 9d80 	lw	a0,-32768\(a1\)
+			3dc: R_MIPS16_LO16	big_external_data_label
+ 3e0:	f000 6d00 	li	a1,0
+			3e0: R_MIPS16_HI16	small_external_data_label
+ 3e4:	f400 35a0 	sll	a1,16
+ 3e8:	f010 9d80 	lw	a0,-32768\(a1\)
+			3e8: R_MIPS16_LO16	small_external_data_label
+ 3ec:	f000 6d00 	li	a1,0
+			3ec: R_MIPS16_HI16	big_external_common
+ 3f0:	f400 35a0 	sll	a1,16
+ 3f4:	f010 9d80 	lw	a0,-32768\(a1\)
+			3f4: R_MIPS16_LO16	big_external_common
+ 3f8:	f000 6d00 	li	a1,0
+			3f8: R_MIPS16_HI16	small_external_common
+ 3fc:	f400 35a0 	sll	a1,16
+ 400:	f010 9d80 	lw	a0,-32768\(a1\)
+			400: R_MIPS16_LO16	small_external_common
+ 404:	f000 6d00 	li	a1,0
+			404: R_MIPS16_HI16	\.bss
+ 408:	f400 35a0 	sll	a1,16
+ 40c:	f010 9d80 	lw	a0,-32768\(a1\)
+			40c: R_MIPS16_LO16	\.bss
+ 410:	f000 6d00 	li	a1,0
+			410: R_MIPS16_HI16	\.sbss
+ 414:	f400 35a0 	sll	a1,16
+ 418:	f010 9d80 	lw	a0,-32768\(a1\)
+			418: R_MIPS16_LO16	\.sbss
+ 41c:	6d01      	li	a1,1
+ 41e:	f400 35a0 	sll	a1,16
+ 422:	9d80      	lw	a0,0\(a1\)
+ 424:	f000 6d01 	li	a1,1
+			424: R_MIPS16_HI16	\.data
+ 428:	f400 35a0 	sll	a1,16
+ 42c:	f000 9d80 	lw	a0,0\(a1\)
+			42c: R_MIPS16_LO16	\.data
+ 430:	f000 6d01 	li	a1,1
+			430: R_MIPS16_HI16	\.data
+ 434:	f400 35a0 	sll	a1,16
+ 438:	f000 9d84 	lw	a0,4\(a1\)
+			438: R_MIPS16_LO16	\.data
+ 43c:	f000 6d01 	li	a1,1
+			43c: R_MIPS16_HI16	big_external_data_label
+ 440:	f400 35a0 	sll	a1,16
+ 444:	f000 9d80 	lw	a0,0\(a1\)
+			444: R_MIPS16_LO16	big_external_data_label
+ 448:	f000 6d01 	li	a1,1
+			448: R_MIPS16_HI16	small_external_data_label
+ 44c:	f400 35a0 	sll	a1,16
+ 450:	f000 9d80 	lw	a0,0\(a1\)
+			450: R_MIPS16_LO16	small_external_data_label
+ 454:	f000 6d01 	li	a1,1
+			454: R_MIPS16_HI16	big_external_common
+ 458:	f400 35a0 	sll	a1,16
+ 45c:	f000 9d80 	lw	a0,0\(a1\)
+			45c: R_MIPS16_LO16	big_external_common
+ 460:	f000 6d01 	li	a1,1
+			460: R_MIPS16_HI16	small_external_common
+ 464:	f400 35a0 	sll	a1,16
+ 468:	f000 9d80 	lw	a0,0\(a1\)
+			468: R_MIPS16_LO16	small_external_common
+ 46c:	f000 6d01 	li	a1,1
+			46c: R_MIPS16_HI16	\.bss
+ 470:	f400 35a0 	sll	a1,16
+ 474:	f000 9d80 	lw	a0,0\(a1\)
+			474: R_MIPS16_LO16	\.bss
+ 478:	f000 6d01 	li	a1,1
+			478: R_MIPS16_HI16	\.sbss
+ 47c:	f400 35a0 	sll	a1,16
+ 480:	f000 9d80 	lw	a0,0\(a1\)
+			480: R_MIPS16_LO16	\.sbss
+ 484:	6d02      	li	a1,2
+ 486:	f400 35a0 	sll	a1,16
+ 48a:	f5b4 9d85 	lw	a0,-23131\(a1\)
+ 48e:	f000 6d02 	li	a1,2
+			48e: R_MIPS16_HI16	\.data
+ 492:	f400 35a0 	sll	a1,16
+ 496:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			496: R_MIPS16_LO16	\.data
+ 49a:	f000 6d02 	li	a1,2
+			49a: R_MIPS16_HI16	\.data
+ 49e:	f400 35a0 	sll	a1,16
+ 4a2:	f5b4 9d89 	lw	a0,-23127\(a1\)
+			4a2: R_MIPS16_LO16	\.data
+ 4a6:	f000 6d02 	li	a1,2
+			4a6: R_MIPS16_HI16	big_external_data_label
+ 4aa:	f400 35a0 	sll	a1,16
+ 4ae:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4ae: R_MIPS16_LO16	big_external_data_label
+ 4b2:	f000 6d02 	li	a1,2
+			4b2: R_MIPS16_HI16	small_external_data_label
+ 4b6:	f400 35a0 	sll	a1,16
+ 4ba:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4ba: R_MIPS16_LO16	small_external_data_label
+ 4be:	f000 6d02 	li	a1,2
+			4be: R_MIPS16_HI16	big_external_common
+ 4c2:	f400 35a0 	sll	a1,16
+ 4c6:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4c6: R_MIPS16_LO16	big_external_common
+ 4ca:	f000 6d02 	li	a1,2
+			4ca: R_MIPS16_HI16	small_external_common
+ 4ce:	f400 35a0 	sll	a1,16
+ 4d2:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4d2: R_MIPS16_LO16	small_external_common
+ 4d6:	f000 6d02 	li	a1,2
+			4d6: R_MIPS16_HI16	\.bss
+ 4da:	f400 35a0 	sll	a1,16
+ 4de:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4de: R_MIPS16_LO16	\.bss
+ 4e2:	f000 6d02 	li	a1,2
+			4e2: R_MIPS16_HI16	\.sbss
+ 4e6:	f400 35a0 	sll	a1,16
+ 4ea:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4ea: R_MIPS16_LO16	\.sbss
+ 4ee:	6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16-hilo.s b/gas/testsuite/gas/mips/mips16-hilo.s
new file mode 100644
index 0000000..cc1e8a0
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-hilo.s
@@ -0,0 +1,346 @@
+# Source file used to test li/addi on MIPS16
+	
+	.set	mips16
+	
+	.data
+data_label:
+	.word	0
+data_label2:
+	.word	0
+	
+	.extern big_external_data_label,1000
+	.extern small_external_data_label,1
+	.comm big_external_common,1000
+	.comm small_external_common,1
+	.lcomm big_local_common,1000
+	.lcomm small_local_common,1
+	
+	.text
+stuff:		
+	li	$4,%hi(0)
+	sll	$4,16
+	addiu	$4,%lo(0)
+	li	$4,%hi(data_label)
+	sll	$4,16
+	addiu	$4,%lo(data_label)
+	li	$4,%hi(data_label2)
+	sll	$4,16
+	addiu	$4,%lo(data_label2)
+	li	$4,%hi(big_external_data_label)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label)
+	li	$4,%hi(small_external_data_label)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label)
+	li	$4,%hi(big_external_common)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common)
+	li	$4,%hi(small_external_common)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common)
+	li	$4,%hi(big_local_common)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common)
+	li	$4,%hi(small_local_common)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common)
+	li	$4,%hi(1)
+	sll	$4,16
+	addiu	$4,%lo(1)
+	li	$4,%hi(data_label+1)
+	sll	$4,16
+	addiu	$4,%lo(data_label+1)
+	li	$4,%hi(data_label2+1)
+	sll	$4,16
+	addiu	$4,%lo(data_label2+1)
+	li	$4,%hi(big_external_data_label+1)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label+1)
+	li	$4,%hi(small_external_data_label+1)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label+1)
+	li	$4,%hi(big_external_common+1)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common+1)
+	li	$4,%hi(small_external_common+1)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common+1)
+	li	$4,%hi(big_local_common+1)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common+1)
+	li	$4,%hi(small_local_common+1)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common+1)
+	li	$4,%hi(0x8000)
+	sll	$4,16
+	addiu	$4,%lo(0x8000)
+	li	$4,%hi(data_label+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(data_label+0x8000)
+	li	$4,%hi(data_label2+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(data_label2+0x8000)
+	li	$4,%hi(big_external_data_label+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label+0x8000)
+	li	$4,%hi(small_external_data_label+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label+0x8000)
+	li	$4,%hi(big_external_common+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common+0x8000)
+	li	$4,%hi(small_external_common+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common+0x8000)
+	li	$4,%hi(big_local_common+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common+0x8000)
+	li	$4,%hi(small_local_common+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common+0x8000)
+	li	$4,%hi(-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(-0x8000)
+	li	$4,%hi(data_label-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(data_label-0x8000)
+	li	$4,%hi(data_label2-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(data_label2-0x8000)
+	li	$4,%hi(big_external_data_label-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label-0x8000)
+	li	$4,%hi(small_external_data_label-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label-0x8000)
+	li	$4,%hi(big_external_common-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common-0x8000)
+	li	$4,%hi(small_external_common-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common-0x8000)
+	li	$4,%hi(big_local_common-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common-0x8000)
+	li	$4,%hi(small_local_common-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common-0x8000)
+	li	$4,%hi(0x10000)
+	sll	$4,16
+	addiu	$4,%lo(0x10000)
+	li	$4,%hi(data_label+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(data_label+0x10000)
+	li	$4,%hi(data_label2+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(data_label2+0x10000)
+	li	$4,%hi(big_external_data_label+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label+0x10000)
+	li	$4,%hi(small_external_data_label+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label+0x10000)
+	li	$4,%hi(big_external_common+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common+0x10000)
+	li	$4,%hi(small_external_common+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common+0x10000)
+	li	$4,%hi(big_local_common+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common+0x10000)
+	li	$4,%hi(small_local_common+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common+0x10000)
+	li	$4,%hi(0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(0x1a5a5)
+	li	$4,%hi(data_label+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(data_label+0x1a5a5)
+	li	$4,%hi(data_label2+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(data_label2+0x1a5a5)
+	li	$4,%hi(big_external_data_label+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label+0x1a5a5)
+	li	$4,%hi(small_external_data_label+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label+0x1a5a5)
+	li	$4,%hi(big_external_common+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common+0x1a5a5)
+	li	$4,%hi(small_external_common+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common+0x1a5a5)
+	li	$4,%hi(big_local_common+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common+0x1a5a5)
+	li	$4,%hi(small_local_common+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common+0x1a5a5)
+	li	$5,%hi(0)
+	sll	$5,16
+	lw	$4,%hi(0)($5)
+	li	$5,%hi(data_label)
+	sll	$5,16
+	lw	$4,%hi(data_label)($5)
+	li	$5,%hi(data_label2)
+	sll	$5,16
+	lw	$4,%hi(data_label2)($5)
+	li	$5,%hi(big_external_data_label)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label)($5)
+	li	$5,%hi(small_external_data_label)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label)($5)
+	li	$5,%hi(big_external_common)
+	sll	$5,16
+	lw	$4,%lo(big_external_common)($5)
+	li	$5,%hi(small_external_common)
+	sll	$5,16
+	lw	$4,%lo(small_external_common)($5)
+	li	$5,%hi(big_local_common)
+	sll	$5,16
+	lw	$4,%lo(big_local_common)($5)
+	li	$5,%hi(small_local_common)
+	sll	$5,16
+	lw	$4,%lo(small_local_common)($5)
+	li	$5,%hi(1)
+	sll	$5,16
+	lw	$4,%lo(1)($5)
+	li	$5,%hi(data_label+1)
+	sll	$5,16
+	lw	$4,%lo(data_label+1)($5)
+	li	$5,%hi(data_label2+1)
+	sll	$5,16
+	lw	$4,%lo(data_label2+1)($5)
+	li	$5,%hi(big_external_data_label+1)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label+1)($5)
+	li	$5,%hi(small_external_data_label+1)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label+1)($5)
+	li	$5,%hi(big_external_common+1)
+	sll	$5,16
+	lw	$4,%lo(big_external_common+1)($5)
+	li	$5,%hi(small_external_common+1)
+	sll	$5,16
+	lw	$4,%lo(small_external_common+1)($5)
+	li	$5,%hi(big_local_common+1)
+	sll	$5,16
+	lw	$4,%lo(big_local_common+1)($5)
+	li	$5,%hi(small_local_common+1)
+	sll	$5,16
+	lw	$4,%lo(small_local_common+1)($5)
+	li	$5,%hi(0x8000)
+	sll	$5,16
+	lw	$4,%lo(0x8000)($5)
+	li	$5,%hi(data_label+0x8000)
+	sll	$5,16
+	lw	$4,%lo(data_label+0x8000)($5)
+	li	$5,%hi(data_label2+0x8000)
+	sll	$5,16
+	lw	$4,%lo(data_label2+0x8000)($5)
+	li	$5,%hi(big_external_data_label+0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label+0x8000)($5)
+	li	$5,%hi(small_external_data_label+0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label+0x8000)($5)
+	li	$5,%hi(big_external_common+0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_external_common+0x8000)($5)
+	li	$5,%hi(small_external_common+0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_external_common+0x8000)($5)
+	li	$5,%hi(big_local_common+0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_local_common+0x8000)($5)
+	li	$5,%hi(small_local_common+0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_local_common+0x8000)($5)
+	li	$5,%hi(-0x8000)
+	sll	$5,16
+	lw	$4,%lo(-0x8000)($5)
+	li	$5,%hi(data_label-0x8000)
+	sll	$5,16
+	lw	$4,%lo(data_label-0x8000)($5)
+	li	$5,%hi(data_label2-0x8000)
+	sll	$5,16
+	lw	$4,%lo(data_label2-0x8000)($5)
+	li	$5,%hi(big_external_data_label-0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label-0x8000)($5)
+	li	$5,%hi(small_external_data_label-0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label-0x8000)($5)
+	li	$5,%hi(big_external_common-0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_external_common-0x8000)($5)
+	li	$5,%hi(small_external_common-0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_external_common-0x8000)($5)
+	li	$5,%hi(big_local_common-0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_local_common-0x8000)($5)
+	li	$5,%hi(small_local_common-0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_local_common-0x8000)($5)
+	li	$5,%hi(0x10000)
+	sll	$5,16
+	lw	$4,%lo(0x10000)($5)
+	li	$5,%hi(data_label+0x10000)
+	sll	$5,16
+	lw	$4,%lo(data_label+0x10000)($5)
+	li	$5,%hi(data_label2+0x10000)
+	sll	$5,16
+	lw	$4,%lo(data_label2+0x10000)($5)
+	li	$5,%hi(big_external_data_label+0x10000)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label+0x10000)($5)
+	li	$5,%hi(small_external_data_label+0x10000)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label+0x10000)($5)
+	li	$5,%hi(big_external_common+0x10000)
+	sll	$5,16
+	lw	$4,%lo(big_external_common+0x10000)($5)
+	li	$5,%hi(small_external_common+0x10000)
+	sll	$5,16
+	lw	$4,%lo(small_external_common+0x10000)($5)
+	li	$5,%hi(big_local_common+0x10000)
+	sll	$5,16
+	lw	$4,%lo(big_local_common+0x10000)($5)
+	li	$5,%hi(small_local_common+0x10000)
+	sll	$5,16
+	lw	$4,%lo(small_local_common+0x10000)($5)
+	li	$5,%hi(0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(0x1a5a5)($5)
+	li	$5,%hi(data_label+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(data_label+0x1a5a5)($5)
+	li	$5,%hi(data_label2+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(data_label2+0x1a5a5)($5)
+	li	$5,%hi(big_external_data_label+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label+0x1a5a5)($5)
+	li	$5,%hi(small_external_data_label+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label+0x1a5a5)($5)
+	li	$5,%hi(big_external_common+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(big_external_common+0x1a5a5)($5)
+	li	$5,%hi(small_external_common+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(small_external_common+0x1a5a5)($5)
+	li	$5,%hi(big_local_common+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(big_local_common+0x1a5a5)($5)
+	li	$5,%hi(small_local_common+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(small_local_common+0x1a5a5)($5)
+
+# align section end to 16-byte boundary for easier testing on multiple targets
+	.p2align 4