aarch64: Add support for sve2p1 tblq instruction.

This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en

5 files changed, 53 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
new file mode 100644
index 0000000..1aa2b39
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 TBLQ instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-6-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
new file mode 100644
index 0000000..0fea325
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
@@ -0,0 +1,18 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `tblq z0.s,{z0.b},z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	tblq z0.b, {z0.b}, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	tblq z0.h, {z0.h}, z0.h
+.*: Info:    	tblq z0.s, {z0.s}, z0.s
+.*: Info:    	tblq z0.d, {z0.d}, z0.d
+.*: Error: expected a single-register list at operand 2 -- `tblq z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected a single-register list at operand 2 -- `tblq z0.s,{z0.s-z1.s},z0.s'
+.*: Error: operand mismatch -- `tblq z0.s,{z31.s},z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	tblq z0.s, {z31.s}, z0.s
+.*: Info:    other valid variant\(s\):
+.*: Info:    	tblq z0.b, {z31.b}, z0.b
+.*: Info:    	tblq z0.h, {z31.h}, z0.h
+.*: Info:    	tblq z0.d, {z31.d}, z0.d
+.*: Error: expected an SVE vector register at operand 3 -- `tblq z0.b,{z0.b},{z31.b}'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
new file mode 100644
index 0000000..0f8300e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
@@ -0,0 +1,6 @@
+tblq z0.s, {z0.b}, z0.b
+tblq z31.b, z0.b, z0.b
+tblq z0.s, {z0.s, z1.s}, z0.s
+tblq z0.s, {z0.s - z1.s}, z0.s
+tblq z0.s, {z31.s}, z0.b
+tblq z0.b, {z0.b}, {z31.b}
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
new file mode 100644
index 0000000..d146903
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -0,0 +1,18 @@
+#name: Test of SVE2.1 TBLQ instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	4400f800 	tblq	z0.b, {z0.b}, z0.b
+.*:	4400f81f 	tblq	z31.b, {z0.b}, z0.b
+.*:	44c0f800 	tblq	z0.d, {z0.d}, z0.d
+.*:	4400fbe0 	tblq	z0.b, {z31.b}, z0.b
+.*:	441ff800 	tblq	z0.b, {z0.b}, z31.b
+.*:	44dffbff 	tblq	z31.d, {z31.d}, z31.d
+.*:	444ff945 	tblq	z5.h, {z10.h}, z15.h
+.*:	4487f861 	tblq	z1.s, {z3.s}, z7.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s
new file mode 100644
index 0000000..d2a0ef5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.s
@@ -0,0 +1,8 @@
+tblq z0.b, {z0.b}, z0.b
+tblq z31.b, {z0.b}, z0.b
+tblq z0.d, {z0.d}, z0.d
+tblq z0.b, {z31.b}, z0.b
+tblq z0.b, {z0.b}, z31.b
+tblq z31.d, {z31.d}, z31.d
+tblq z5.h, {z10.h}, z15.h
+tblq z1.s, {z3.s}, z7.s