RISC-V: Add support for XCVelw extension in CV32E40P

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett682@gmail.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvelw` instruction
	class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* doc/c-riscv.texi: Note XCVelw as an additional ISA extension
	for CORE-V.
	* testsuite/gas/riscv/cv-elw-fail.d: New test.
	* testsuite/gas/riscv/cv-elw-fail.l: New test.
	* testsuite/gas/riscv/cv-elw-fail.s: New test.
	* testsuite/gas/riscv/cv-elw-fail-march.d: New test.
	* testsuite/gas/riscv/cv-elw-fail-march.l: New test.
	* testsuite/gas/riscv/cv-elw-fail-march.s: New test.
	* testsuite/gas/riscv/cv-elw-pass.d: New test.
	* testsuite/gas/riscv/cv-elw-pass.s: New test.
	* testsuite/gas/riscv/march-help.l: Add xcvelw string.

opcodes/ChangeLog:

	* riscv-opc.c: (riscv_opcode) Add event load instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Add corresponding MATCH and MASK
	instruction opcode macros.
	* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XCVELW.

10 files changed, 191 insertions, 0 deletions

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 4edd874..7908083 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -750,6 +750,11 @@ The Xcvalu extension provides instructions for general ALU operations.
 
 It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
 
+@item Xcvelw
+The Xcvelw extension provides instructions for event load word operations.
+
+It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
+
 @item XTheadBa
 The XTheadBa extension provides instructions for address calculations.
 
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.d b/gas/testsuite/gas/riscv/cv-elw-fail-march.d
new file mode 100644
index 0000000..5a3a6db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: cv-elw-fail-march.s
+#error_output: cv-elw-fail-march.l
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.l b/gas/testsuite/gas/riscv/cv-elw-fail-march.l
new file mode 100644
index 0000000..760a71b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.l
@@ -0,0 +1,38 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `cv.elw x5,-2048\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x5,0\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x5,20\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x5,2047\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x31,2047\(x31\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x0,0\(x0\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x1,1024\(x1\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x2,1024\(x2\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x3,1024\(x3\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x4,1024\(x4\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x5,1024\(x5\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x6,1024\(x6\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x7,1024\(x7\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x8,1024\(x8\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x9,1024\(x9\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x10,1024\(x10\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x11,1024\(x11\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x12,1024\(x12\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x13,1024\(x13\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x14,1024\(x14\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x15,1024\(x15\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x16,1024\(x16\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x17,1024\(x17\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x18,1024\(x18\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x19,1024\(x19\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x20,1024\(x20\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x21,1024\(x21\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x22,1024\(x22\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x23,1024\(x23\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x24,1024\(x24\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x25,1024\(x25\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x26,1024\(x26\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x27,1024\(x27\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x28,1024\(x28\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x29,1024\(x29\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x30,1024\(x30\)', extension `xcvelw' required
+.*: Error: unrecognized opcode `cv.elw x31,1024\(x31\)', extension `xcvelw' required
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail-march.s b/gas/testsuite/gas/riscv/cv-elw-fail-march.s
new file mode 100644
index 0000000..5784884
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail-march.s
@@ -0,0 +1,41 @@
+target:
+    # Immediate Boundary Tests
+    cv.elw x5,-2048(x6)
+    cv.elw x5,0(x6)
+    cv.elw x5,20(x6)
+    cv.elw x5,2047(x6)
+    cv.elw x31,2047(x31)
+
+    # Register Boundary Tests
+    cv.elw x0,0(x0)
+    cv.elw x1,1024(x1)
+    cv.elw x2,1024(x2)
+    cv.elw x3,1024(x3)
+    cv.elw x4,1024(x4)
+    cv.elw x5,1024(x5)
+    cv.elw x6,1024(x6)
+    cv.elw x7,1024(x7)
+    cv.elw x8,1024(x8)
+    cv.elw x9,1024(x9)
+    cv.elw x10,1024(x10)
+    cv.elw x11,1024(x11)
+    cv.elw x12,1024(x12)
+    cv.elw x13,1024(x13)
+    cv.elw x14,1024(x14)
+    cv.elw x15,1024(x15)
+    cv.elw x16,1024(x16)
+    cv.elw x17,1024(x17)
+    cv.elw x18,1024(x18)
+    cv.elw x19,1024(x19)
+    cv.elw x20,1024(x20)
+    cv.elw x21,1024(x21)
+    cv.elw x22,1024(x22)
+    cv.elw x23,1024(x23)
+    cv.elw x24,1024(x24)
+    cv.elw x25,1024(x25)
+    cv.elw x26,1024(x26)
+    cv.elw x27,1024(x27)
+    cv.elw x28,1024(x28)
+    cv.elw x29,1024(x29)
+    cv.elw x30,1024(x30)
+    cv.elw x31,1024(x31)
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.d b/gas/testsuite/gas/riscv/cv-elw-fail.d
new file mode 100644
index 0000000..d7fd1d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_xcvelw
+#source: cv-elw-fail.s
+#error_output: cv-elw-fail.l
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.l b/gas/testsuite/gas/riscv/cv-elw-fail.l
new file mode 100644
index 0000000..4d3f15b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cv.elw x5,-2049\(x6\)'
+.*: Error: illegal operands `cv.elw x5,2048\(x6\)'
+.*: Error: illegal operands `cv.elw x-1,1024\(x-1\)'
+.*: Error: illegal operands `cv.elw x32,1024\(x32\)'
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/cv-elw-fail.s b/gas/testsuite/gas/riscv/cv-elw-fail.s
new file mode 100644
index 0000000..4ce1222
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-fail.s
@@ -0,0 +1,8 @@
+target:
+    # Immediate Boundary Tests
+    cv.elw x5,-2049(x6)
+    cv.elw x5,2048(x6)
+
+    # Register Boundary Tests
+    cv.elw x-1,1024(x-1)
+    cv.elw x32,1024(x32)
diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.d b/gas/testsuite/gas/riscv/cv-elw-pass.d
new file mode 100644
index 0000000..0451149
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-pass.d
@@ -0,0 +1,46 @@
+#as: -march=rv32i_xcvelw
+#source: cv-elw-pass.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[  ]+0:[	]+8003628b[ 	]+cv.elw[	]+t0,-2048\(t1\)
+[  ]+4:[	]+0003628b[ 	]+cv.elw[	]+t0,0\(t1\)
+[  ]+8:[	]+0143628b[ 	]+cv.elw[	]+t0,20\(t1\)
+[  ]+c:[	]+7ff3628b[ 	]+cv.elw[	]+t0,2047\(t1\)
+[  ]+10:[	]+7fffef8b[ 	]+cv.elw[	]+t6,2047\(t6\)
+[  ]+14:[	]+0000600b[ 	]+cv.elw[	]+zero,0\(zero\) # 0 <target>
+[  ]+18:[	]+4000e08b[ 	]+cv.elw[	]+ra,1024\(ra\)
+[  ]+1c:[	]+4001610b[ 	]+cv.elw[	]+sp,1024\(sp\)
+[  ]+20:[	]+4001e18b[ 	]+cv.elw[	]+gp,1024\(gp\)
+[  ]+24:[	]+4002620b[ 	]+cv.elw[	]+tp,1024\(tp\) # 400 <target\+0x400>
+[  ]+28:[	]+4002e28b[ 	]+cv.elw[	]+t0,1024\(t0\)
+[  ]+2c:[	]+4003630b[ 	]+cv.elw[	]+t1,1024\(t1\)
+[  ]+30:[	]+4003e38b[ 	]+cv.elw[	]+t2,1024\(t2\)
+[  ]+34:[	]+4004640b[ 	]+cv.elw[	]+s0,1024\(s0\)
+[  ]+38:[	]+4004e48b[ 	]+cv.elw[	]+s1,1024\(s1\)
+[  ]+3c:[	]+4005650b[ 	]+cv.elw[	]+a0,1024\(a0\)
+[  ]+40:[	]+4005e58b[ 	]+cv.elw[	]+a1,1024\(a1\)
+[  ]+44:[	]+4006660b[ 	]+cv.elw[	]+a2,1024\(a2\)
+[  ]+48:[	]+4006e68b[ 	]+cv.elw[	]+a3,1024\(a3\)
+[  ]+4c:[	]+4007670b[ 	]+cv.elw[	]+a4,1024\(a4\)
+[  ]+50:[	]+4007e78b[ 	]+cv.elw[	]+a5,1024\(a5\)
+[  ]+54:[	]+4008680b[ 	]+cv.elw[	]+a6,1024\(a6\)
+[  ]+58:[	]+4008e88b[ 	]+cv.elw[	]+a7,1024\(a7\)
+[  ]+5c:[	]+4009690b[ 	]+cv.elw[	]+s2,1024\(s2\)
+[  ]+60:[	]+4009e98b[ 	]+cv.elw[	]+s3,1024\(s3\)
+[  ]+64:[	]+400a6a0b[ 	]+cv.elw[	]+s4,1024\(s4\)
+[  ]+68:[	]+400aea8b[ 	]+cv.elw[	]+s5,1024\(s5\)
+[  ]+6c:[	]+400b6b0b[ 	]+cv.elw[	]+s6,1024\(s6\)
+[  ]+70:[	]+400beb8b[ 	]+cv.elw[	]+s7,1024\(s7\)
+[  ]+74:[	]+400c6c0b[ 	]+cv.elw[	]+s8,1024\(s8\)
+[  ]+78:[	]+400cec8b[ 	]+cv.elw[	]+s9,1024\(s9\)
+[  ]+7c:[	]+400d6d0b[ 	]+cv.elw[	]+s10,1024\(s10\)
+[  ]+80:[	]+400ded8b[ 	]+cv.elw[	]+s11,1024\(s11\)
+[  ]+84:[	]+400e6e0b[ 	]+cv.elw[	]+t3,1024\(t3\)
+[  ]+88:[	]+400eee8b[ 	]+cv.elw[	]+t4,1024\(t4\)
+[  ]+8c:[	]+400f6f0b[ 	]+cv.elw[	]+t5,1024\(t5\)
+[  ]+90:[	]+400fef8b[ 	]+cv.elw[	]+t6,1024\(t6\)
diff --git a/gas/testsuite/gas/riscv/cv-elw-pass.s b/gas/testsuite/gas/riscv/cv-elw-pass.s
new file mode 100644
index 0000000..5784884
--- /dev/null
+++ b/gas/testsuite/gas/riscv/cv-elw-pass.s
@@ -0,0 +1,41 @@
+target:
+    # Immediate Boundary Tests
+    cv.elw x5,-2048(x6)
+    cv.elw x5,0(x6)
+    cv.elw x5,20(x6)
+    cv.elw x5,2047(x6)
+    cv.elw x31,2047(x31)
+
+    # Register Boundary Tests
+    cv.elw x0,0(x0)
+    cv.elw x1,1024(x1)
+    cv.elw x2,1024(x2)
+    cv.elw x3,1024(x3)
+    cv.elw x4,1024(x4)
+    cv.elw x5,1024(x5)
+    cv.elw x6,1024(x6)
+    cv.elw x7,1024(x7)
+    cv.elw x8,1024(x8)
+    cv.elw x9,1024(x9)
+    cv.elw x10,1024(x10)
+    cv.elw x11,1024(x11)
+    cv.elw x12,1024(x12)
+    cv.elw x13,1024(x13)
+    cv.elw x14,1024(x14)
+    cv.elw x15,1024(x15)
+    cv.elw x16,1024(x16)
+    cv.elw x17,1024(x17)
+    cv.elw x18,1024(x18)
+    cv.elw x19,1024(x19)
+    cv.elw x20,1024(x20)
+    cv.elw x21,1024(x21)
+    cv.elw x22,1024(x22)
+    cv.elw x23,1024(x23)
+    cv.elw x24,1024(x24)
+    cv.elw x25,1024(x25)
+    cv.elw x26,1024(x26)
+    cv.elw x27,1024(x27)
+    cv.elw x28,1024(x28)
+    cv.elw x29,1024(x29)
+    cv.elw x30,1024(x30)
+    cv.elw x31,1024(x31)
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index c575483..90ff73e 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -105,6 +105,7 @@ All available -march extensions for RISC-V:
 	svpbmt                                  1.0
 	xcvmac                                  1.0
 	xcvalu                                  1.0
+	xcvelw                                  1.0
 	xtheadba                                1.0
 	xtheadbb                                1.0
 	xtheadbs                                1.0