diff options
| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 15:08:32 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:32:12 +0800 |
| commit | 832cdeeccb063073ba2893ec63060773fc8b98ae (patch) | |
| tree | dc295d1f0f64428d1fb916b24f0ae615dabb4f22 /gas | |
| parent | b4cf88da83fbbceecdec7ad4e1addddfe2c2b76d (diff) | |
| download | binutils-832cdeeccb063073ba2893ec63060773fc8b98ae.zip binutils-832cdeeccb063073ba2893ec63060773fc8b98ae.tar.gz binutils-832cdeeccb063073ba2893ec63060773fc8b98ae.tar.bz2 | |
RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds mask instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
mask instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VMPOPCM): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector.d | 26 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector.s | 30 |
2 files changed, 56 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 2c80eeb..03d8ede 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -1592,3 +1592,29 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c6861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+cc861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+c4861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+66842257[ ]+th.vmcpy.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+6e422257[ ]+th.vmclr.m[ ]+v4 +[ ]+[0-9a-f]+:[ ]+7e422257[ ]+th.vmset.m[ ]+v4 +[ ]+[0-9a-f]+:[ ]+76842257[ ]+th.vmnot.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+66862257[ ]+th.vmand.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+76862257[ ]+th.vmnand.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+62862257[ ]+th.vmandnot.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6e862257[ ]+th.vmxor.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+6a862257[ ]+th.vmor.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+7a862257[ ]+th.vmnor.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+72862257[ ]+th.vmornot.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+7e862257[ ]+th.vmxnor.mm[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+52c02557[ ]+th.vmpopc.m[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+56c02557[ ]+th.vmfirst.m[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+5a80a257[ ]+th.vmsbf.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5a81a257[ ]+th.vmsif.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5a812257[ ]+th.vmsof.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5a882257[ ]+th.viota.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+5a08a257[ ]+th.vid.v[ ]+v4 +[ ]+[0-9a-f]+:[ ]+50c02557[ ]+th.vmpopc.m[ ]+a0,v12,v0.t +[ ]+[0-9a-f]+:[ ]+54c02557[ ]+th.vmfirst.m[ ]+a0,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5880a257[ ]+th.vmsbf.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+5881a257[ ]+th.vmsif.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+58812257[ ]+th.vmsof.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+58882257[ ]+th.viota.m[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+5808a257[ ]+th.vid.v[ ]+v4,v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index 71f83a2..1c1c27c 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -1656,3 +1656,33 @@ th.vfwredsum.vs v4, v8, v12 th.vfwredosum.vs v4, v8, v12, v0.t th.vfwredsum.vs v4, v8, v12, v0.t + + # Aliases + th.vmcpy.m v4, v8 + th.vmclr.m v4 + th.vmset.m v4 + th.vmnot.m v4, v8 + + th.vmand.mm v4, v8, v12 + th.vmnand.mm v4, v8, v12 + th.vmandnot.mm v4, v8, v12 + th.vmxor.mm v4, v8, v12 + th.vmor.mm v4, v8, v12 + th.vmnor.mm v4, v8, v12 + th.vmornot.mm v4, v8, v12 + th.vmxnor.mm v4, v8, v12 + + th.vmpopc.m a0, v12 + th.vmfirst.m a0, v12 + th.vmsbf.m v4, v8 + th.vmsif.m v4, v8 + th.vmsof.m v4, v8 + th.viota.m v4, v8 + th.vid.v v4 + th.vmpopc.m a0, v12, v0.t + th.vmfirst.m a0, v12, v0.t + th.vmsbf.m v4, v8, v0.t + th.vmsif.m v4, v8, v0.t + th.vmsof.m v4, v8, v0.t + th.viota.m v4, v8, v0.t + th.vid.v v4, v0.t |