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authorSrinath Parvathaneni <srinath.parvathaneni@arm.com>2024-07-08 16:36:44 +0100
committerRichard Earnshaw <rearnsha@arm.com>2024-07-12 15:41:56 +0100
commit7bdb051fd62ca70aa2cf549441b7728d20a3a631 (patch)
tree2285ed9d79fd35d898fb1fae79f365372eafd146 /gas
parent6ab366f2643d13507e53e85684dc5b5a5e14b54b (diff)
downloadbinutils-7bdb051fd62ca70aa2cf549441b7728d20a3a631.zip
binutils-7bdb051fd62ca70aa2cf549441b7728d20a3a631.tar.gz
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aarch64: Add support for sme2.1 zero instructions.
This patch adds support for following sme2.1 zero instructions and the spec is available here [1]. 1. ZERO (single-vector). 2. ZERO (double-vector). 3. ZERO (quad-vector). The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler for most of the sme and sve instructions. But for few of the sme2.1 zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory. To address this a bit "F_VG_REQ" is introduced in this patch, on setting F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept instruction operand only having VECTOR GROUP symbols. [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
Diffstat (limited to 'gas')
-rw-r--r--gas/testsuite/gas/aarch64/sme-4-illegal.l2
-rw-r--r--gas/testsuite/gas/aarch64/sme2p1-5-bad.d4
-rw-r--r--gas/testsuite/gas/aarch64/sme2p1-5-bad.l103
-rw-r--r--gas/testsuite/gas/aarch64/sme2p1-5-bad.s54
-rw-r--r--gas/testsuite/gas/aarch64/sme2p1-5.d54
-rw-r--r--gas/testsuite/gas/aarch64/sme2p1-5.s54
6 files changed, 270 insertions, 1 deletions
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index a9e9852..db52529 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -1,5 +1,5 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero za'
+[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `zero za'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za8\.d}'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za8.d}'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za2\.h}'
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.d b/gas/testsuite/gas/aarch64/sme2p1-5-bad.d
new file mode 100644
index 0000000..86a6834
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.d
@@ -0,0 +1,4 @@
+#name: Negative test of SME2.1 ZERO instructions.
+#as: -march=armv9.4-a+sme2p1
+#source: sme2p1-5-bad.s
+#error_output: sme2p1-5-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.l b/gas/testsuite/gas/aarch64/sme2p1-5-bad.l
new file mode 100644
index 0000000..959864a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.l
@@ -0,0 +1,103 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `zero za.s\[w8,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 0, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w14,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w14, 0, vgx2\]
+.*: Error: expected a selection register in the range w8-w11 at operand 1 -- `zero za.d\[w2,7,vgx2\]'
+.*: Error: immediate offset out of range 0 to 7 at operand 1 -- `zero za.d\[w11,17,vgx2\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.d\[w9,4,vgx3\]'
+.*: Error: operand mismatch -- `zero za.h\[w10,3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 3\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0, vgx4\]
+.*: Error: operand mismatch -- `zero za.b\[w1,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0, vgx4\]
+.*: Error: operand mismatch -- `zero za.q\[w8,17,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 17, vgx2\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w11,7,vgx3\]'
+.*: Error: expected a constant immediate offset at operand 1 -- `zero za.s\[w9,vg\]'
+.*: Error: operand mismatch -- `zero za.b\[w10,3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 3\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0:1\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:1\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:1\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:1\]
+.*: Error: operand mismatch -- `zero za.b\[w8,4:5\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 4:5\]
+.*: Error: operand mismatch -- `zero za.b\[w11,1:5\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w11, 1:5\]
+.*: Error: operand mismatch -- `zero za.h\[w9,2:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 2:13\]
+.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.h\[w10,16:7\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w1,0:1,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:1, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w8,6:7,vg\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.q\[w9,12:13,vgx3\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:1,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:1, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w1,0:1,vgx3\]'
+.*: Error: operand mismatch -- `zero za.b\[w8,16:17,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 16:17, vgx4\]
+.*: Error: operand mismatch -- `zero za.q\[w9,12:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 12:13\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.s\[w18,0:3,\]'
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3\]
+.*: Error: operand mismatch -- `zero za.b\[w8,8:11\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 8:11\]
+.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.b\[w11,18:1,vgx3\]'
+.*: Error: operand mismatch -- `zero za.h\[w9,4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 4\]
+.*: Error: operand mismatch -- `zero za.h\[w10,10:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 10:13\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 14:17, vgx2\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]'
+.*: Error: operand mismatch -- `zero za.h\[w9,0:3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 0:3\]
+.*: Error: expected a constant immediate offset at operand 1 -- `zero za.q\[w10,vgx2\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx4\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3, vgx4\]
+.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 14:17, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w9,0:3,vgx3\]'
+.*: Error: operand mismatch -- `zero za.q\[w10,4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 4\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.s b/gas/testsuite/gas/aarch64/sme2p1-5-bad.s
new file mode 100644
index 0000000..5b69634
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.s
@@ -0,0 +1,54 @@
+/* ZERO (single-vector). */
+zero za.s[w8, 0, vgx2]
+zero za.b[w14, 0, vgx2]
+zero za.d[w2, 7, vgx2]
+zero za.d[w11, 17, vgx2]
+zero za.d[w9, 4, vgx3]
+zero za.h[w10, 3]
+
+zero za.s[w18, 0, vgx4]
+zero za.b[w1, 0, vgx4]
+zero za.q[w8, 17, vgx2]
+zero za.h[w11, 7, vgx3]
+zero za.s[w9, vg]
+zero za.b[w10, 3]
+
+/* ZERO (double-vector). */
+zero za.s[w18, 0:1]
+zero za.s[w1, 0:1]
+zero za.b[w8, 4:5]
+zero za.b[w11, 1:5]
+zero za.h[w9, 2:13]
+zero za.h[w10, 16:7]
+
+zero za.s[w18, 0:3, vgx2]
+zero za.b[w1, 0:1, vgx4]
+zero za.h[w8, 6:7, vg]
+zero za.q[w9, 12:13, vgx3]
+
+zero za.s[w18, 0:1, vgx4]
+zero za.h[w1, 0:1, vgx3]
+zero za.b[w8, 16:17, vgx4]
+zero za.q[w9, 12:13]
+
+/* ZERO (quad-vector). */
+zero za.s[w18, 0:3,]
+zero za.s[w1, 0:3]
+zero za.b[w8, 8:11]
+zero za.b[w11, 18:1, vgx3]
+zero za.h[w9, 4]
+zero za.h[w10, 10:13]
+
+zero za.s[w18, 0:3, vgx2]
+zero za.s[w1, 0:3, vgx2]
+zero za.b[w8, 14:17, vgx2]
+zero za.b[w11, 4:7, vg]
+zero za.h[w9, 0:3]
+zero za.q[w10, vgx2]
+
+zero za.s[w18, 0:3, vgx4]
+zero za.s[w1, 0:3, vgx4]
+zero za.b[w8, 14:17, vgx4]
+zero za.b[w11, 4:7, vg]
+zero za.h[w9, 0:3, vgx3]
+zero za.q[w10, 4]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5.d b/gas/testsuite/gas/aarch64/sme2p1-5.d
new file mode 100644
index 0000000..f63a171
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5.d
@@ -0,0 +1,54 @@
+#name: Test of SME2.1 ZERO instructions.
+#as: -march=armv9.4-a+sme2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c00c0000 zero za.d\[w8, 0, vgx2\]
+.*: c00c6000 zero za.d\[w11, 0, vgx2\]
+.*: c00c0007 zero za.d\[w8, 7, vgx2\]
+.*: c00c6007 zero za.d\[w11, 7, vgx2\]
+.*: c00c2004 zero za.d\[w9, 4, vgx2\]
+.*: c00c4003 zero za.d\[w10, 3, vgx2\]
+.*: c00e0000 zero za.d\[w8, 0, vgx4\]
+.*: c00e6000 zero za.d\[w11, 0, vgx4\]
+.*: c00e0007 zero za.d\[w8, 7, vgx4\]
+.*: c00e6007 zero za.d\[w11, 7, vgx4\]
+.*: c00e2004 zero za.d\[w9, 4, vgx4\]
+.*: c00e4003 zero za.d\[w10, 3, vgx4\]
+.*: c00c8000 zero za.d\[w8, 0:1\]
+.*: c00ce000 zero za.d\[w11, 0:1\]
+.*: c00c8007 zero za.d\[w8, 14:15\]
+.*: c00ce007 zero za.d\[w11, 14:15\]
+.*: c00ca001 zero za.d\[w9, 2:3\]
+.*: c00cc003 zero za.d\[w10, 6:7\]
+.*: c00d0000 zero za.d\[w8, 0:1, vgx2\]
+.*: c00d6000 zero za.d\[w11, 0:1, vgx2\]
+.*: c00d0003 zero za.d\[w8, 6:7, vgx2\]
+.*: c00d2001 zero za.d\[w9, 2:3, vgx2\]
+.*: c00d8000 zero za.d\[w8, 0:1, vgx4\]
+.*: c00de000 zero za.d\[w11, 0:1, vgx4\]
+.*: c00d8003 zero za.d\[w8, 6:7, vgx4\]
+.*: c00da001 zero za.d\[w9, 2:3, vgx4\]
+.*: c00e8000 zero za.d\[w8, 0:3\]
+.*: c00ee000 zero za.d\[w11, 0:3\]
+.*: c00e8002 zero za.d\[w8, 8:11\]
+.*: c00ee002 zero za.d\[w11, 8:11\]
+.*: c00ea001 zero za.d\[w9, 4:7\]
+.*: c00ec000 zero za.d\[w10, 0:3\]
+.*: c00f0000 zero za.d\[w8, 0:3, vgx2\]
+.*: c00f6000 zero za.d\[w11, 0:3, vgx2\]
+.*: c00f0001 zero za.d\[w8, 4:7, vgx2\]
+.*: c00f6001 zero za.d\[w11, 4:7, vgx2\]
+.*: c00f2000 zero za.d\[w9, 0:3, vgx2\]
+.*: c00f4001 zero za.d\[w10, 4:7, vgx2\]
+.*: c00f8000 zero za.d\[w8, 0:3, vgx4\]
+.*: c00fe000 zero za.d\[w11, 0:3, vgx4\]
+.*: c00f8001 zero za.d\[w8, 4:7, vgx4\]
+.*: c00fe001 zero za.d\[w11, 4:7, vgx4\]
+.*: c00fa000 zero za.d\[w9, 0:3, vgx4\]
+.*: c00fc001 zero za.d\[w10, 4:7, vgx4\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5.s b/gas/testsuite/gas/aarch64/sme2p1-5.s
new file mode 100644
index 0000000..bd25682
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5.s
@@ -0,0 +1,54 @@
+/* ZERO (single-vector). */
+zero za.d[w8, 0, vgx2]
+zero za.d[w11, 0, vgx2]
+zero za.d[w8, 7, vgx2]
+zero za.d[w11, 7, vgx2]
+zero za.d[w9, 4, vgx2]
+zero za.d[w10, 3, vgx2]
+
+zero za.d[w8, 0, vgx4]
+zero za.d[w11, 0, vgx4]
+zero za.d[w8, 7, vgx4]
+zero za.d[w11, 7, vgx4]
+zero za.d[w9, 4, vgx4]
+zero za.d[w10, 3, vgx4]
+
+/* ZERO (double-vector). */
+zero za.d[w8, 0:1]
+zero za.d[w11, 0:1]
+zero za.d[w8, 14:15]
+zero za.d[w11, 14:15]
+zero za.d[w9, 2:3]
+zero za.d[w10, 6:7]
+
+zero za.d[w8, 0:1, vgx2]
+zero za.d[w11, 0:1, vgx2]
+zero za.d[w8, 6:7, vgx2]
+zero za.d[w9, 2:3, vgx2]
+
+zero za.d[w8, 0:1, vgx4]
+zero za.d[w11, 0:1, vgx4]
+zero za.d[w8, 6:7, vgx4]
+zero za.d[w9, 2:3, vgx4]
+
+/* ZERO (quad-vector). */
+zero za.d[w8, 0:3]
+zero za.d[w11, 0:3]
+zero za.d[w8, 8:11]
+zero za.d[w11, 8:11]
+zero za.d[w9, 4:7]
+zero za.d[w10, 0:3]
+
+zero za.d[w8, 0:3, vgx2]
+zero za.d[w11, 0:3, vgx2]
+zero za.d[w8, 4:7, vgx2]
+zero za.d[w11, 4:7, vgx2]
+zero za.d[w9, 0:3, vgx2]
+zero za.d[w10, 4:7, vgx2]
+
+zero za.d[w8, 0:3, vgx4]
+zero za.d[w11, 0:3, vgx4]
+zero za.d[w8, 4:7, vgx4]
+zero za.d[w11, 4:7, vgx4]
+zero za.d[w9, 0:3, vgx4]
+zero za.d[w10, 4:7, vgx4]