x86: Support Intel AVX VNNI

Intel AVX VNNI instructions are marked with CpuVEX_PREFIX.  Without the
pseudo {vex} prefix, mnemonics of Intel VNNI instructions are encoded
with the EVEX prefix.  The pseudo {vex} prefix can be used to encode
mnemonics of Intel VNNI instructions with the VEX prefix.

gas/

	* NEWS: Add Intel AVX VNNI.
	* config/tc-i386.c (cpu_arch): Add .avx_vnni and noavx_vnni.
	(cpu_flags_match): Support CpuVEX_PREFIX.
	* doc/c-i386.texi: Document .avx_vnni, noavx_vnni and how to
	encode Intel VNNI instructions with VEX prefix.
	* testsuite/gas/i386/avx-vnni.d: New file.
	* testsuite/gas/i386/avx-vnni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run AVX VNNI tests.

opcodes/

	* i386-dis.c (PREFIX_VEX_0F3850): New.
	(PREFIX_VEX_0F3851): Likewise.
	(PREFIX_VEX_0F3852): Likewise.
	(PREFIX_VEX_0F3853): Likewise.
	(VEX_W_0F3850_P_2): Likewise.
	(VEX_W_0F3851_P_2): Likewise.
	(VEX_W_0F3852_P_2): Likewise.
	(VEX_W_0F3853_P_2): Likewise.
	(prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
	PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
	(vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
	VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
	(putop): Add support for "XV" to print "{vex3}" pseudo prefix.
	* i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
	CPU_UNKNOWN_FLAGS.  Add CPU_AVX_VNNI_FLAGS and
	CPU_ANY_AVX_VNNI_FLAGS.
	(cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
	* i386-opc.h (CpuAVX_VNNI): New.
	(CpuVEX_PREFIX): Likewise.
	(i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
	* i386-opc.tbl: Add Intel AVX VNNI instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

5 files changed, 137 insertions, 0 deletions

diff --git a/gas/testsuite/gas/i386/avx-vnni.d b/gas/testsuite/gas/i386/avx-vnni.d
new file mode 100644
index 0000000..6d6e779
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-vnni.d
@@ -0,0 +1,43 @@
+#objdump: -dw
+#name: i386 AVX VNNI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 f2 5d 08 50 d2    	vpdpbusd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	62 f2 5d 08 50 d2    	vpdpbusd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 d2       	\{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 d2       	\{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 d2       	\{vex3\} vpdpbusd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 11       	\{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 11       	\{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 11       	\{vex3\} vpdpbusd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	62 f2 5d 08 52 d2    	vpdpwssd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	62 f2 5d 08 52 d2    	vpdpwssd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 d2       	\{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 d2       	\{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 d2       	\{vex3\} vpdpwssd %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 11       	\{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 11       	\{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 11       	\{vex3\} vpdpwssd \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	62 f2 5d 08 51 d2    	vpdpbusds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	62 f2 5d 08 51 d2    	vpdpbusds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 d2       	\{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 d2       	\{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 d2       	\{vex3\} vpdpbusds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 11       	\{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 11       	\{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 11       	\{vex3\} vpdpbusds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	62 f2 5d 08 53 d2    	vpdpwssds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	62 f2 5d 08 53 d2    	vpdpwssds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 d2       	\{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 d2       	\{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 d2       	\{vex3\} vpdpwssds %xmm2,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 11       	\{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 11       	\{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 11       	\{vex3\} vpdpwssds \(%ecx\),%xmm4,%xmm2
+ +[a-f0-9]+:	62 f2 5d 08 50 d2    	vpdpbusd %xmm2,%xmm4,%xmm2
+#pass
diff --git a/gas/testsuite/gas/i386/avx-vnni.s b/gas/testsuite/gas/i386/avx-vnni.s
new file mode 100644
index 0000000..4ddc733
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-vnni.s
@@ -0,0 +1,22 @@
+	.allow_index_reg
+
+.macro test_insn mnemonic
+	\mnemonic	%xmm2, %xmm4, %xmm2
+	{evex} \mnemonic %xmm2, %xmm4, %xmm2
+	{vex}  \mnemonic %xmm2, %xmm4, %xmm2
+	{vex2} \mnemonic %xmm2, %xmm4, %xmm2
+	{vex3} \mnemonic %xmm2, %xmm4, %xmm2
+	{vex}  \mnemonic (%ecx), %xmm4, %xmm2
+	{vex2} \mnemonic (%ecx), %xmm4, %xmm2
+	{vex3} \mnemonic (%ecx), %xmm4, %xmm2
+.endm
+
+	.text
+_start:
+	test_insn vpdpbusd
+	test_insn vpdpwssd
+	test_insn vpdpbusds
+	test_insn vpdpwssds
+
+	.arch .avx_vnni
+	 vpdpbusd	%xmm2, %xmm4, %xmm2
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index a761767..f572767 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -458,6 +458,7 @@ if [gas_32_check] then {
     run_dump_test "avx512_bf16"
     run_dump_test "avx512_bf16_vl"
     run_list_test "avx512_bf16_vl-inval"
+    run_dump_test "avx-vnni"
     run_list_test "sg"
     run_dump_test "clzero"
     run_dump_test "disassem"
@@ -1075,6 +1076,7 @@ if [gas_64_check] then {
     run_dump_test "x86-64-avx512_bf16"
     run_dump_test "x86-64-avx512_bf16_vl"
     run_list_test "x86-64-avx512_bf16_vl-inval"
+    run_dump_test "x86-64-avx-vnni"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni.d b/gas/testsuite/gas/i386/x86-64-avx-vnni.d
new file mode 100644
index 0000000..ebb0ebf
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-vnni.d
@@ -0,0 +1,47 @@
+#objdump: -dw
+#name: x86-64 AVX VNNI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	62 d2 5d 08 50 d4    	vpdpbusd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	62 d2 5d 08 50 d4    	vpdpbusd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 50 d4       	\{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 50 d4       	\{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 50 d4       	\{vex3\} vpdpbusd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 11       	\{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 11       	\{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 50 11       	\{vex3\} vpdpbusd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	62 b2 5d 08 50 d6    	vpdpbusd %xmm22,%xmm4,%xmm2
+ +[a-f0-9]+:	62 d2 5d 08 52 d4    	vpdpwssd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	62 d2 5d 08 52 d4    	vpdpwssd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 52 d4       	\{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 52 d4       	\{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 52 d4       	\{vex3\} vpdpwssd %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 11       	\{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 11       	\{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 52 11       	\{vex3\} vpdpwssd \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	62 b2 5d 08 52 d6    	vpdpwssd %xmm22,%xmm4,%xmm2
+ +[a-f0-9]+:	62 d2 5d 08 51 d4    	vpdpbusds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	62 d2 5d 08 51 d4    	vpdpbusds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 51 d4       	\{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 51 d4       	\{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 51 d4       	\{vex3\} vpdpbusds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 11       	\{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 11       	\{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 51 11       	\{vex3\} vpdpbusds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	62 b2 5d 08 51 d6    	vpdpbusds %xmm22,%xmm4,%xmm2
+ +[a-f0-9]+:	62 d2 5d 08 53 d4    	vpdpwssds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	62 d2 5d 08 53 d4    	vpdpwssds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 53 d4       	\{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 53 d4       	\{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 c2 59 53 d4       	\{vex3\} vpdpwssds %xmm12,%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 11       	\{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 11       	\{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	c4 e2 59 53 11       	\{vex3\} vpdpwssds \(%rcx\),%xmm4,%xmm2
+ +[a-f0-9]+:	62 b2 5d 08 53 d6    	vpdpwssds %xmm22,%xmm4,%xmm2
+ +[a-f0-9]+:	62 d2 5d 08 50 d4    	vpdpbusd %xmm12,%xmm4,%xmm2
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-vnni.s b/gas/testsuite/gas/i386/x86-64-avx-vnni.s
new file mode 100644
index 0000000..7f47bf6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-vnni.s
@@ -0,0 +1,23 @@
+	.allow_index_reg
+
+.macro test_insn mnemonic
+	\mnemonic	 %xmm12, %xmm4, %xmm2
+	{evex} \mnemonic %xmm12, %xmm4, %xmm2
+	{vex}  \mnemonic %xmm12, %xmm4, %xmm2
+	{vex2} \mnemonic %xmm12, %xmm4, %xmm2
+	{vex3} \mnemonic %xmm12, %xmm4, %xmm2
+	{vex}  \mnemonic (%rcx), %xmm4, %xmm2
+	{vex2} \mnemonic (%rcx), %xmm4, %xmm2
+	{vex3} \mnemonic (%rcx), %xmm4, %xmm2
+	\mnemonic	 %xmm22, %xmm4, %xmm2
+.endm
+
+	.text
+_start:
+	test_insn vpdpbusd
+	test_insn vpdpwssd
+	test_insn vpdpbusds
+	test_insn vpdpwssds
+
+	.arch .avx_vnni
+	vpdpbusd	%xmm12, %xmm4, %xmm2