diff options
author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:02:03 +0100 |
---|---|---|
committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:38:48 +0100 |
commit | 524e985281588b929b75c9dc5adf56c19de1d0b8 (patch) | |
tree | 8cb3a966c1d203452026243bb7fd56a847d5f898 /gas/testsuite | |
parent | 98043d5fae27fa31e65e421ba1aef18732b2acd5 (diff) | |
download | binutils-524e985281588b929b75c9dc5adf56c19de1d0b8.zip binutils-524e985281588b929b75c9dc5adf56c19de1d0b8.tar.gz binutils-524e985281588b929b75c9dc5adf56c19de1d0b8.tar.bz2 |
aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
This patch adds missing contraints to FEAT_B16B16 sve2 instructions
bfclamp, bfmla and bfmls and add negative tests for all the bfloat
instructions.
The bfloat16-invalid.* testcases are renamed to bfloat16-1-invalid.*
to maintain consistency in the testsuite.
The bfloat16-1-invalid.* tests are modified so that "selected
processor does not support" is generated by the assembler, since
+b16b16 is not passed in the command line.
The bfloat16-2-invalid.* testcase includes the wrong operands
bfloat16 tests.
Diffstat (limited to 'gas/testsuite')
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-1-invalid.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-1-invalid.l | 11 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-1-invalid.s | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-1.d | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-1.s | 7 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-2-invalid.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-2-invalid.l | 265 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-2-invalid.s | 147 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-bad.l | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-invalid.d | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-invalid.l | 8 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/bfloat16-invalid.s | 13 |
12 files changed, 456 insertions, 26 deletions
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d new file mode 100644 index 0000000..531a597 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d @@ -0,0 +1,4 @@ +#name: Negative test with missing +b16b16 flag. +#as: -march=armv9.4-a +#source: bfloat16-1-invalid.s +#error_output: bfloat16-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.l new file mode 100644 index 0000000..3609fa2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.l @@ -0,0 +1,11 @@ +.*: Assembler messages: +.*: Error: selected processor does not support `bfadd z0.h,p0/m,z0.h,z0.h' +.*: Error: selected processor does not support `bfmax z0.h,p0/m,z0.h,z0.h' +.*: Error: selected processor does not support `bfmaxnm z0.h,p0/m,z0.h,z0.h' +.*: Error: selected processor does not support `bfmin z0.h,p0/m,z0.h,z0.h' +.*: Error: selected processor does not support `bfminnm z0.h,p0/m,z0.h,z0.h' +.*: Error: selected processor does not support `bfmul z0.h,p0/m,z0.h,z0.h' +.*: Error: selected processor does not support `bfsub z0.h,p0/m,z0.h,z0.h' +.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h' +.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]' +.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]' diff --git a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.s b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.s new file mode 100644 index 0000000..ee3b760 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.s @@ -0,0 +1,10 @@ +bfadd z0.h, p0/m, z0.h, z0.h +bfmax z0.h, p0/m, z0.h, z0.h +bfmaxnm z0.h, p0/m, z0.h, z0.h +bfmin z0.h, p0/m, z0.h, z0.h +bfminnm z0.h, p0/m, z0.h, z0.h +bfmul z0.h, p0/m, z0.h, z0.h +bfsub z0.h, p0/m, z0.h, z0.h +bfclamp z3.h,z4.h,z16.h +bfmla z3.h,z16.h,z6.h[7] +bfmls z3.h,z16.h,z6.h[7] diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/bfloat16-1.d index 4f1df80..51f7e6c 100644 --- a/gas/testsuite/gas/aarch64/bfloat16-1.d +++ b/gas/testsuite/gas/aarch64/bfloat16-1.d @@ -104,3 +104,9 @@ .*: 65020604 bfsub z4.h, z16.h, z2.h .*: 65010688 bfsub z8.h, z20.h, z1.h .*: 65000710 bfsub z16.h, z24.h, z0.h +.*: 0420bca3 movprfx z3, z5 +.*: 64302483 bfclamp z3.h, z4.h, z16.h +.*: 0420bca3 movprfx z3, z5 +.*: 647e0a03 bfmla z3.h, z16.h, z6.h\[7\] +.*: 0420bca3 movprfx z3, z5 +.*: 647e0e03 bfmls z3.h, z16.h, z6.h\[7\] diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.s b/gas/testsuite/gas/aarch64/bfloat16-1.s index b896913..be8fee9 100644 --- a/gas/testsuite/gas/aarch64/bfloat16-1.s +++ b/gas/testsuite/gas/aarch64/bfloat16-1.s @@ -110,4 +110,9 @@ bfsub z4.h, z16.h, z2.h bfsub z8.h, z20.h, z1.h bfsub z16.h, z24.h, z0.h - +movprfx z3, z5 +bfclamp z3.h, z4.h, z16.h +movprfx z3, z5 +bfmla z3.h, z16.h, z6.h[7] +movprfx z3, z5 +bfmls z3.h, z16.h, z6.h[7] diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d new file mode 100644 index 0000000..1cd2745 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d @@ -0,0 +1,4 @@ +#name: Test Bfloat16 instructions with wrong operand combinations +#as: -march=armv9.4-a+b16b16 +#source: bfloat16-2-invalid.s +#error_output: bfloat16-2-invalid.l diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l new file mode 100644 index 0000000..5da96c7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l @@ -0,0 +1,265 @@ +.*: Assembler messages: +.*: Error: operand mismatch -- `bfadd z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfadd z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfadd z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfadd z0.h,p8/m,z0.h,z16.h' +.*: Error: operand 3 must be the same register as operand 1 -- `bfadd z31.h,p0/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfadd z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfadd z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfadd z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfadd z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfmax z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmax z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmax z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfmax z0.h,p8/m,z0.h,z16.h' +.*: Error: operand 3 must be the same register as operand 1 -- `bfmax z31.h,p0/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmax z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfmax z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmax z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfmax z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfmaxnm z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfmaxnm z0.h,p8/m,z0.h,z16.h' +.*: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm z31.h,p0/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfmaxnm z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmaxnm z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfmaxnm z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfmin z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmin z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmin z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfmin z0.h,p8/m,z0.h,z16.h' +.*: Error: operand 3 must be the same register as operand 1 -- `bfmin z31.h,p0/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmin z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfmin z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmin z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfmin z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfminnm z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfminnm z0.h,p8/m,z0.h,z16.h' +.*: Error: operand 3 must be the same register as operand 1 -- `bfminnm z31.h,p0/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfminnm z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfminnm z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfminnm z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfmla z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmla z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmla z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfmla z0.h,p8/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmla z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfmla z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmla z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfmla z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfmls z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmls z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmls z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfmls z0.h,p8/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmls z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfmls z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmls z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfmls z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfmul z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmul z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmul z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfmul z0.h,p8/m,z0.h,z16.h' +.*: Error: operand 3 must be the same register as operand 1 -- `bfmul z31.h,p0/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfmul z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfmul z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfmul z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfmul z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfsub z0.s,p0/m,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfsub z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.h,z16.h' +.*: Info: did you mean this\? +.*: Info: bfsub z0.h, p0/m, z0.h, z16.h +.*: Error: p0-p7 expected at operand 2 -- `bfsub z0.h,p8/m,z0.h,z16.h' +.*: Error: operand 3 must be the same register as operand 1 -- `bfsub z31.h,p0/m,z0.h,z16.h' +.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.s,z16.h' +.*: Info: did you mean this\? +.*: Info: bfsub z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.h,z16.d' +.*: Info: did you mean this\? +.*: Info: bfsub z0.h, p0/m, z0.h, z16.h +.*: Error: operand mismatch -- `bfsub z31.d,p7/m,z31.d,z31.d' +.*: Info: did you mean this\? +.*: Info: bfsub z31.h, p7/m, z31.h, z31.h +.*: Error: operand mismatch -- `bfadd z0.b,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfadd z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfadd z0.s,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfadd z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfadd z0.h,z0.d,z0.h' +.*: Info: did you mean this\? +.*: Info: bfadd z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfadd z0.h,z0.h,z0.b' +.*: Info: did you mean this\? +.*: Info: bfadd z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfadd z31.b,z31.s,z31.d' +.*: Info: did you mean this\? +.*: Info: bfadd z31.h, z31.h, z31.h +.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h},z0.h,z0.h' +.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h-z0.h},z0.h' +.*: Error: comma expected between operands at operand 3 -- `bfadd z0.h,z0.h' +.*: Error: operand mismatch -- `bfclamp z0.b,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfclamp z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfclamp z0.s,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfclamp z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfclamp z0.h,z0.d,z0.h' +.*: Info: did you mean this\? +.*: Info: bfclamp z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfclamp z0.h,z0.h,z0.b' +.*: Info: did you mean this\? +.*: Info: bfclamp z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfclamp z31.b,z31.s,z31.d' +.*: Info: did you mean this\? +.*: Info: bfclamp z31.h, z31.h, z31.h +.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h},z0.h,z0.h' +.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h-z0.h},z0.h' +.*: Error: comma expected between operands at operand 3 -- `bfclamp z0.h,z0.h' +.*: Error: operand mismatch -- `bfmla z0.b,z0.h,z0.h\[0\]' +.*: Info: did you mean this\? +.*: Info: bfmla z0.h, z0.h, z0.h\[0\] +.*: Error: operand mismatch -- `bfmla z0.s,z0.h,z0.h\[6\]' +.*: Info: did you mean this\? +.*: Info: bfmla z0.h, z0.h, z0.h\[6\] +.*: Error: operand mismatch -- `bfmla z0.h,z0.d,z0.h\[8\]' +.*: Info: did you mean this\? +.*: Info: bfmla z0.h, z0.h, z0.h\[8\] +.*: Error: operand mismatch -- `bfmla z0.h,z0.h,z0.b\[2\]' +.*: Info: did you mean this\? +.*: Info: bfmla z0.h, z0.h, z0.h\[2\] +.*: Error: operand mismatch -- `bfmla z31.b,z31.s,z31.d\[8\]' +.*: Info: did you mean this\? +.*: Info: bfmla z31.h, z31.h, z31.h\[8\] +.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h},z0.h,z0.h\[1\]' +.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h-z0.h},z0.h\[2\]' +.*: Error: expected an SVE predicate register at operand 2 -- `bfmla z0.h,z0.h\[3\]' +.*: Error: operand mismatch -- `bfmls z0.b,z0.h,z0.h\[0\]' +.*: Info: did you mean this\? +.*: Info: bfmls z0.h, z0.h, z0.h\[0\] +.*: Error: operand mismatch -- `bfmls z0.s,z0.h,z0.h\[6\]' +.*: Info: did you mean this\? +.*: Info: bfmls z0.h, z0.h, z0.h\[6\] +.*: Error: operand mismatch -- `bfmls z0.h,z0.d,z0.h\[8\]' +.*: Info: did you mean this\? +.*: Info: bfmls z0.h, z0.h, z0.h\[8\] +.*: Error: operand mismatch -- `bfmls z0.h,z0.h,z0.b\[2\]' +.*: Info: did you mean this\? +.*: Info: bfmls z0.h, z0.h, z0.h\[2\] +.*: Error: operand mismatch -- `bfmls z31.b,z31.s,z31.d\[8\]' +.*: Info: did you mean this\? +.*: Info: bfmls z31.h, z31.h, z31.h\[8\] +.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h},z0.h,z0.h\[1\]' +.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h-z0.h},z0.h\[2\]' +.*: Error: expected an SVE predicate register at operand 2 -- `bfmls z0.h,z0.h\[3\]' +.*: Error: operand mismatch -- `bfmul z0.b,z0.h,z0.h\[0\]' +.*: Info: did you mean this\? +.*: Info: bfmul z0.h, z0.h, z0.h\[0\] +.*: Error: operand mismatch -- `bfmul z0.s,z0.h,z0.h\[6\]' +.*: Info: did you mean this\? +.*: Info: bfmul z0.h, z0.h, z0.h\[6\] +.*: Error: operand mismatch -- `bfmul z0.h,z0.d,z0.h\[8\]' +.*: Info: did you mean this\? +.*: Info: bfmul z0.h, z0.h, z0.h\[8\] +.*: Error: operand mismatch -- `bfmul z0.h,z0.h,z0.b\[2\]' +.*: Info: did you mean this\? +.*: Info: bfmul z0.h, z0.h, z0.h\[2\] +.*: Error: operand mismatch -- `bfmul z31.b,z31.s,z31.d\[8\]' +.*: Info: did you mean this\? +.*: Info: bfmul z31.h, z31.h, z31.h\[8\] +.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h},z0.h,z0.h\[1\]' +.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h-z0.h},z0.h\[2\]' +.*: Error: expected an SVE predicate register at operand 2 -- `bfmul z0.h,z0.h\[3\]' +.*: Error: operand mismatch -- `bfsub z0.b,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfsub z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfsub z0.s,z0.h,z0.h' +.*: Info: did you mean this\? +.*: Info: bfsub z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfsub z0.h,z0.d,z0.h' +.*: Info: did you mean this\? +.*: Info: bfsub z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfsub z0.h,z0.h,z0.b' +.*: Info: did you mean this\? +.*: Info: bfsub z0.h, z0.h, z0.h +.*: Error: operand mismatch -- `bfsub z31.b,z31.s,z31.d' +.*: Info: did you mean this\? +.*: Info: bfsub z31.h, z31.h, z31.h +.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h},z0.h,z0.h' +.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h-z0.h},z0.h' +.*: Error: comma expected between operands at operand 3 -- `bfsub z0.h,z0.h' +.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z1.h,z3.h,z16.h' +.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmla z10.h,z16.h,z3.h\[7\]' +.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfmls z1.h,z3.h,z3.h\[7\]' +.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z4,z5' +.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z2.h,z3.h,z4.h' diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s new file mode 100644 index 0000000..d690f12 --- /dev/null +++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s @@ -0,0 +1,147 @@ +bfadd z0.s, p0/m, z0.h, z16.h +bfadd z0.h, p0/z, z0.h, z16.h +bfadd z0.h, p8/m, z0.h, z16.h +bfadd z31.h, p0/m, z0.h, z16.h +bfadd z0.h, p0/z, z0.s, z16.h +bfadd z0.h, p0/z, z0.h, z16.d +bfadd z31.d, p7/m, z31.d, z31.d + +bfmax z0.s, p0/m, z0.h, z16.h +bfmax z0.h, p0/z, z0.h, z16.h +bfmax z0.h, p8/m, z0.h, z16.h +bfmax z31.h, p0/m, z0.h, z16.h +bfmax z0.h, p0/z, z0.s, z16.h +bfmax z0.h, p0/z, z0.h, z16.d +bfmax z31.d, p7/m, z31.d, z31.d + +bfmaxnm z0.s, p0/m, z0.h, z16.h +bfmaxnm z0.h, p0/z, z0.h, z16.h +bfmaxnm z0.h, p8/m, z0.h, z16.h +bfmaxnm z31.h, p0/m, z0.h, z16.h +bfmaxnm z0.h, p0/z, z0.s, z16.h +bfmaxnm z0.h, p0/z, z0.h, z16.d +bfmaxnm z31.d, p7/m, z31.d, z31.d + +bfmin z0.s, p0/m, z0.h, z16.h +bfmin z0.h, p0/z, z0.h, z16.h +bfmin z0.h, p8/m, z0.h, z16.h +bfmin z31.h, p0/m, z0.h, z16.h +bfmin z0.h, p0/z, z0.s, z16.h +bfmin z0.h, p0/z, z0.h, z16.d +bfmin z31.d, p7/m, z31.d, z31.d + +bfminnm z0.s, p0/m, z0.h, z16.h +bfminnm z0.h, p0/z, z0.h, z16.h +bfminnm z0.h, p8/m, z0.h, z16.h +bfminnm z31.h, p0/m, z0.h, z16.h +bfminnm z0.h, p0/z, z0.s, z16.h +bfminnm z0.h, p0/z, z0.h, z16.d +bfminnm z31.d, p7/m, z31.d, z31.d + +bfmla z0.s, p0/m, z0.h, z16.h +bfmla z0.h, p0/z, z0.h, z16.h +bfmla z0.h, p8/m, z0.h, z16.h +bfmla z31.h, p0/m, z0.h, z16.h +bfmla z0.h, p0/z, z0.s, z16.h +bfmla z0.h, p0/z, z0.h, z16.d +bfmla z31.d, p7/m, z31.d, z31.d + +bfmls z0.s, p0/m, z0.h, z16.h +bfmls z0.h, p0/z, z0.h, z16.h +bfmls z0.h, p8/m, z0.h, z16.h +bfmls z31.h, p0/m, z0.h, z16.h +bfmls z0.h, p0/z, z0.s, z16.h +bfmls z0.h, p0/z, z0.h, z16.d +bfmls z31.d, p7/m, z31.d, z31.d + +bfmul z0.s, p0/m, z0.h, z16.h +bfmul z0.h, p0/z, z0.h, z16.h +bfmul z0.h, p8/m, z0.h, z16.h +bfmul z31.h, p0/m, z0.h, z16.h +bfmul z0.h, p0/z, z0.s, z16.h +bfmul z0.h, p0/z, z0.h, z16.d +bfmul z31.d, p7/m, z31.d, z31.d + +bfsub z0.s, p0/m, z0.h, z16.h +bfsub z0.h, p0/z, z0.h, z16.h +bfsub z0.h, p8/m, z0.h, z16.h +bfsub z31.h, p0/m, z0.h, z16.h +bfsub z0.h, p0/z, z0.s, z16.h +bfsub z0.h, p0/z, z0.h, z16.d +bfsub z31.d, p7/m, z31.d, z31.d + +bfadd z0.b, z0.h, z0.h +bfadd z31.h, z0.h, z0.h +bfadd z0.s, z0.h, z0.h +bfadd z0.h, z0.d, z0.h +bfadd z0.h, z0.h, z0.b +bfadd z31.b, z31.s, z31.d +bfadd {z0.h}, z0.h, z0.h +bfadd {z0.h - z0.h}, z0.h +bfadd z0.h, z0.h + +bfclamp z0.b, z0.h, z0.h +bfclamp z31.h, z0.h, z0.h +bfclamp z0.s, z0.h, z0.h +bfclamp z0.h, z0.d, z0.h +bfclamp z0.h, z0.h, z0.b +bfclamp z31.b, z31.s, z31.d +bfclamp {z0.h}, z0.h, z0.h +bfclamp {z0.h - z0.h}, z0.h +bfclamp z0.h, z0.h + +bfmla z0.b, z0.h, z0.h[0] +bfmla z31.h, z0.h, z0.h[3] +bfmla z0.s, z0.h, z0.h[6] +bfmla z0.h, z0.d, z0.h[8] +bfmla z0.h, z0.h, z0.b[2] +bfmla z31.b, z31.s, z31.d[8] +bfmla {z0.h}, z0.h, z0.h[1] +bfmla {z0.h - z0.h}, z0.h[2] +bfmla z0.h, z0.h[3] + +bfmls z0.b, z0.h, z0.h[0] +bfmls z31.h, z0.h, z0.h[3] +bfmls z0.s, z0.h, z0.h[6] +bfmls z0.h, z0.d, z0.h[8] +bfmls z0.h, z0.h, z0.b[2] +bfmls z31.b, z31.s, z31.d[8] +bfmls {z0.h}, z0.h, z0.h[1] +bfmls {z0.h - z0.h}, z0.h[2] +bfmls z0.h, z0.h[3] + +bfmul z0.b, z0.h, z0.h[0] +bfmul z31.h, z0.h, z0.h[3] +bfmul z0.s, z0.h, z0.h[6] +bfmul z0.h, z0.d, z0.h[8] +bfmul z0.h, z0.h, z0.b[2] +bfmul z31.b, z31.s, z31.d[8] +bfmul {z0.h}, z0.h, z0.h[1] +bfmul {z0.h - z0.h}, z0.h[2] +bfmul z0.h, z0.h[3] + +bfsub z0.b, z0.h, z0.h +bfsub z31.h, z0.h, z0.h +bfsub z0.s, z0.h, z0.h +bfsub z0.h, z0.d, z0.h +bfsub z0.h, z0.h, z0.b +bfsub z31.b, z31.s, z31.d +bfsub {z0.h}, z0.h, z0.h +bfsub {z0.h - z0.h}, z0.h +bfsub z0.h, z0.h + +bfmla z0.h, p0/m, z4.h, z16.h +movprfx z3, z5 +bfclamp z1.h, z3.h, z16.h + +movprfx z3, z5 +bfmla z10.h, z16.h, z3.h[7] + +movprfx z3, z5 +bfmls z1.h, z3.h, z3.h[7] + +movprfx z2, z3 +movprfx z4, z5 +bfclamp z2.h, z3.h, z4.h +bfmla z4.h, z5.h, z6.h[7] +bfmls z3.h, z1.h, z4.h[7] diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.l b/gas/testsuite/gas/aarch64/bfloat16-bad.l index 1519a29..d4098bf 100644 --- a/gas/testsuite/gas/aarch64/bfloat16-bad.l +++ b/gas/testsuite/gas/aarch64/bfloat16-bad.l @@ -95,3 +95,6 @@ .*: Error: selected processor does not support `bfsub z4.h,z16.h,z2.h' .*: Error: selected processor does not support `bfsub z8.h,z20.h,z1.h' .*: Error: selected processor does not support `bfsub z16.h,z24.h,z0.h' +.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h' +.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]' +.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]' diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-invalid.d deleted file mode 100644 index 8f24dc6..0000000 --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.d +++ /dev/null @@ -1,4 +0,0 @@ -#name: Test Bfloat16 instructions with wrong operand combinations -#as: -march=armv9.4-a -#source: bfloat16-invalid.s -#error_output: bfloat16-invalid.l diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-invalid.l deleted file mode 100644 index 0b1354a..0000000 --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l +++ /dev/null @@ -1,8 +0,0 @@ -.*: Assembler messages: -[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfadd .* -[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmax .* -[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm .* -[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmin .* -[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfminnm .* -[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmul .* -[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfsub .* diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.s b/gas/testsuite/gas/aarch64/bfloat16-invalid.s deleted file mode 100644 index a5bdfc8..0000000 --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.s +++ /dev/null @@ -1,13 +0,0 @@ -bfadd z0.h, p0/m, z1.h, z0.h - -bfmax z0.h, p0/m, z1.h, z0.h - -bfmaxnm z0.h, p0/m, z1.h, z0.h - -bfmin z0.h, p0/m, z1.h, z0.h - -bfminnm z0.h, p0/m, z1.h, z0.h - -bfmul z0.h, p0/m, z1.h, z0.h - -bfsub z0.h, p0/m, z1.h, z0.h |