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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-08-12 06:16:51 +0900 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-03 04:04:35 +0000 |
| commit | 7b4f240762ffa03e65e17cb7dee807bc1628c24a (patch) | |
| tree | f428de64dfdf15773b3c37b78d99796ebf2a1b8c /gas/expr.h | |
| parent | 61233edc75c8aaa003e7cbe5e129faf6bb7b9126 (diff) | |
| download | binutils-7b4f240762ffa03e65e17cb7dee807bc1628c24a.zip binutils-7b4f240762ffa03e65e17cb7dee807bc1628c24a.tar.gz binutils-7b4f240762ffa03e65e17cb7dee807bc1628c24a.tar.bz2 | |
RISC-V: Assign DWARF numbers to vector registers
This commit assigns DWARF register numbers to vector registers (v0-v31:
96..127) to implement RISC-V DWARF Specification version 1.0-rc4
(now in the frozen state):
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4
binutils/ChangeLog:
* dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers
96..127 to vector registers v0-v31.
gas/ChangeLog:
* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support
vector registers.
* testsuite/gas/riscv/dw-regnums.s: Add vector registers to the
DWARF register number test.
* testsuite/gas/riscv/dw-regnums.d: Likewise.
Diffstat (limited to 'gas/expr.h')
0 files changed, 0 insertions, 0 deletions