Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well.

	PR 25224
bfd	* Makefile.am: Add z80-elf target support.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
	* elf32-z80.c: New file.
	* archures.c: Add new z80 architectures: eZ80 and Z180.
	* coffcode.h: Likewise.
	* cpu-z80.c: Likewise.
	* bfd-in2.h: Likewise plus additional Z80 relocations.
	* coff-z80.c: Add new relocations for Z80 target and local label check.

gas	* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
	for assembler code generated by SDCC. Add new relocation types. Add
	z80-elf target support.
	* config/tc-z80.h: Add z80-elf target support. Enable dollar local
	labels. Local labels starts from ".L".
	* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
	* testsuite/gas/all/fwdexp.s: Likewise.
	* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
	* testsuite/gas/z80/z80.exp: Add new tests
	* testsuite/gas/z80/dollar.d: New file.
	* testsuite/gas/z80/dollar.s: New file.
	* testsuite/gas/z80/ez80_adl_all.d: New file.
	* testsuite/gas/z80/ez80_adl_all.s: New file.
	* testsuite/gas/z80/ez80_adl_suf.d: New file.
	* testsuite/gas/z80/ez80_isuf.s: New file.
	* testsuite/gas/z80/ez80_z80_all.d: New file.
	* testsuite/gas/z80/ez80_z80_all.s: New file.
	* testsuite/gas/z80/ez80_z80_suf.d: New file.
	* testsuite/gas/z80/r800_extra.d: New file.
	* testsuite/gas/z80/r800_extra.s: New file.
	* testsuite/gas/z80/r800_ii8.d: New file.
	* testsuite/gas/z80/r800_z80_doc.d: New file.
	* testsuite/gas/z80/z180.d: New file.
	* testsuite/gas/z80/z180.s: New file.
	* testsuite/gas/z80/z180_z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.s: New file.
	* testsuite/gas/z80/z80_ii8.d: New file.
	* testsuite/gas/z80/z80_ii8.s: New file.
	* testsuite/gas/z80/z80_in_f_c.d: New file.
	* testsuite/gas/z80/z80_in_f_c.s: New file.
	* testsuite/gas/z80/z80_op_ii_ld.d: New file.
	* testsuite/gas/z80/z80_op_ii_ld.s: New file.
	* testsuite/gas/z80/z80_out_c_0.d: New file.
	* testsuite/gas/z80/z80_out_c_0.s: New file.
	* testsuite/gas/z80/z80_reloc.d: New file.
	* testsuite/gas/z80/z80_reloc.s: New file.
	* testsuite/gas/z80/z80_sli.d: New file.
	* testsuite/gas/z80/z80_sli.s: New file.

ld	* Makefile.am: Add new target z80-elf
	* configure.tgt: Likewise.
	* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
	* emulparams/elf32z80.sh: New file.
	* emultempl/z80elf.em: Likewise.
	* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
	* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/arch_r800.d: Likewise.
	* testsuite/ld-z80/arch_z180.d: Likewise.
	* testsuite/ld-z80/arch_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z180.d: Likewise.
	* testsuite/ld-z80/labels.s: Likewise.
	* testsuite/ld-z80/relocs.s: Likewise.
	* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_b_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80.d: Likewise.
	* testsuite/ld-z80/z80.exp: Likewise.

opcodes	* z80-dis.c: Add support for eZ80 and Z80 instructions.

1 files changed, 45 insertions, 2 deletions

diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 8957f20..15b33fd 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -630,7 +630,10 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @ifset Z80
 
 @emph{Target Z80 options:}
-  [@b{-z80}] [@b{-r800}]
+  [@b{-z80}]|[@b{-z180}]|[@b{-r800}]|[@b{-ez80}]|[@b{-ez80-adl}]
+  [@b{-strict}]|[@b{-full}]
+  [@b{-with-inst=@var{INST}[,...]}] [@b{-Wnins @var{INST}[,...]}]
+  [@b{-without-inst=@var{INST}[,...]}] [@b{-Fins @var{INST}[,...]}]
   [@b{ -ignore-undocumented-instructions}] [@b{-Wnud}]
   [@b{ -ignore-unportable-instructions}] [@b{-Wnup}]
   [@b{ -warn-undocumented-instructions}] [@b{-Wud}]
@@ -1943,10 +1946,34 @@ Xtensa processor.
 The following options are available when @value{AS} is configured for
 a Z80 family processor.
 @table @gcctabopt
+
 @item -z80
 Assemble for Z80 processor.
 @item -r800
 Assemble for R800 processor.
+@item -z180
+Assemble for Z180 processor.
+@item -ez80
+Assemble for eZ80 processor in Z80 memory mode by default.
+@item -ez80-adl
+Assemble for eZ80 processor in ADL memory mode by default.
+
+@item  @code{-colonless}
+Accept colonless labels. All names at line begin are treated as labels.
+@item  @code{-sdcc}
+Accept assembler code produces by SDCC.
+
+@item  @code{-strict}
+Accept documented instructions only.
+@item  @code{-full}
+Accept all known Z80 instructions.
+@item  @code{-with-inst=INST[,...]}
+@itemx @code{-Wnins INST[,...]}
+Enable specified undocumented instruction(s).
+@item  @code{-without-inst=INST[,...]}
+@itemx @code{-Fins INST[,...]}
+Disable specified undocumented instruction(s).
+
 @item  -ignore-undocumented-instructions
 @itemx -Wnud
 Assemble undocumented Z80 instructions that also work on R800 without warning.
@@ -1966,6 +1993,22 @@ Treat all undocumented instructions as errors.
 @itemx -Fup
 Treat undocumented Z80 instructions that do not work on R800 as errors.
 @end table
+
+Folowing undocumented instructions may be enabled/disabled by
+@code{-with-inst}/@code{-without-inst}:
+@table @gcctabopt
+@item  @code{idx-reg-halves}
+All operations with halves of index registers (IXL, IXH, IYL, IYH).
+@item  @code{sli}
+SLI or SLL instruction.
+@item  @code{op-ii-ld}
+Istructions like @code{<op> (<ii>+<d>),<r>}, where @code{<op>}
+is shift or bit manipulation instruction (RLC, SLA, SET, RES...).
+@item @code{in-f-c}
+Instruction @code{IN F,(C)}.
+@item @code{out-c-0}
+Instruction @code{OUT (C),0}
+@end table
 @end ifset
 
 @c man end
@@ -6770,7 +6813,7 @@ If you @code{.set} a global symbol, the value stored in the object
 file is the last value stored into it.
 
 @ifset Z80
-On Z80 @code{set} is a real instruction, use
+On Z80 @code{set} is a real instruction, use @code{.set} or
 @samp{@var{symbol} defl @var{expression}} instead.
 @end ifset