aarch64: Add the SME2 ADD and SUB instructions

Add support for the SME2 ADD. SUB, FADD and FSUB instructions.
SUB and FSUB have the same form as ADD and FADD, except that
ADD also has a 2-operand accumulating form.

The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the
64-bit FADD/FSUB instructions require FEAT_SME_F64F64.

These are the first instructions to have tied register list
operands, as opposed to tied single registers.

The parse_operands change prevents unsuffixed Z registers (width==-1)
from being treated as though they had an Advanced SIMD-style suffix
(.4s etc.).  It means that:

  Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'

becomes:

  Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'

1 files changed, 2 insertions, 1 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 652fd4e..5e02315 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6659,6 +6659,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_Zm_16:
 	case AARCH64_OPND_SVE_Zn:
 	case AARCH64_OPND_SVE_Zt:
+	case AARCH64_OPND_SME_Zm:
 	  reg_type = REG_TYPE_Z;
 	  goto vector_reg;
 
@@ -6811,7 +6812,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 		  goto failure;
 		}
 
-	      if (vectype.width != 0 && *str != ',')
+	      if ((int) vectype.width > 0 && *str != ',')
 		{
 		  set_fatal_syntax_error
 		    (_("expected element type rather than vector type"));