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author | Jan Beulich <jbeulich@novell.com> | 2017-11-23 11:04:18 +0100 |
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committer | Jan Beulich <jbeulich@suse.com> | 2017-11-23 11:04:18 +0100 |
commit | 65f3ed048fa0741e874c7aa372f9ddba153a2949 (patch) | |
tree | 1ebbe1a6a298a49a6b68bd2a1d602095a44c6005 /gas/config | |
parent | 43083a502b8d658b8d096111e54afcc73b0215a4 (diff) | |
download | binutils-65f3ed048fa0741e874c7aa372f9ddba153a2949.zip binutils-65f3ed048fa0741e874c7aa372f9ddba153a2949.tar.gz binutils-65f3ed048fa0741e874c7aa372f9ddba153a2949.tar.bz2 |
x86: fix AVX-512 16-bit addressing
Despite EVEX encodings not being available in real and VM86 modes,
16-bit addressing still needs to be handled properly for 16-bit
protected mode as well as 16-bit addressing in 32-bit mode. Neither
should displacements be dropped silently by the assembler, nor should
the disassembler fail to correctly scale 8-bit displacements.
Diffstat (limited to 'gas/config')
-rw-r--r-- | gas/config/tc-i386.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 4b602d4..f623e82 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4798,12 +4798,8 @@ check_VecOperands (const insn_template *t) i.types[op].bitfield.vec_disp8 = 1; else { - /* Vector insn can only have Vec_Disp8/Disp32 in - 32/64bit modes, and Vec_Disp8/Disp16 in 16bit - mode. */ + /* Vector insn doesn't allow plain Disp8. */ i.types[op].bitfield.disp8 = 0; - if (flag_code != CODE_16BIT) - i.types[op].bitfield.disp16 = 0; } } else if (flag_code != CODE_16BIT) |