gas/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (output_insn): Support Intel Merom New
	Instructions.

	* gas/config/tc-i386.h (CpuMNI): New.
	(CpuUnknownFlags): Add CpuMNI.

gas/testsuite/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add merom and x86-64-merom.

	* gas/i386/merom.d: New file.
	* gas/i386/merom.s: Likewise.
	* gas/i386/x86-64-merom.d: Likewise.
	* gas/i386/x86-64-merom.s: Likewise.

include/opcode/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel Merom New Instructions.

opcodes/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.

2 files changed, 25 insertions, 10 deletions

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 337149e..f42a9a4 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3474,23 +3474,31 @@ output_insn ()
       /* Output normal instructions here.  */
       char *p;
       unsigned char *q;
+      unsigned int prefix;
 
-      /* All opcodes on i386 have either 1 or 2 bytes.  We may use one
-	 more higher byte to specify a prefix the instruction
-	 requires.  */
-      if ((i.tm.base_opcode & 0xff0000) != 0)
+      /* All opcodes on i386 have either 1 or 2 bytes.  Merom New
+	 Instructions have 3 bytes.  We may use one more higher byte
+	 to specify a prefix the instruction requires.  */
+      if ((i.tm.cpu_flags & CpuMNI) != 0)
 	{
+	  if (i.tm.base_opcode & 0xff000000)
+	    {
+	      prefix = (i.tm.base_opcode >> 24) & 0xff;
+	      goto check_prefix;
+	    }
+	}
+      else if ((i.tm.base_opcode & 0xff0000) != 0)
+	{
+	  prefix = (i.tm.base_opcode >> 16) & 0xff;
 	  if ((i.tm.cpu_flags & CpuPadLock) != 0)
 	    {
-	      unsigned int prefix;
-	      prefix = (i.tm.base_opcode >> 16) & 0xff;
-
+check_prefix:
 	      if (prefix != REPE_PREFIX_OPCODE
 		  || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
 		add_prefix (prefix);
 	    }
 	  else
-	    add_prefix ((i.tm.base_opcode >> 16) & 0xff);
+	    add_prefix (prefix);
 	}
 
       /* The prefix bytes.  */
@@ -3512,7 +3520,13 @@ output_insn ()
 	}
       else
 	{
-	  p = frag_more (2);
+	  if ((i.tm.cpu_flags & CpuMNI) != 0)
+	    {
+	      p = frag_more (3);
+	      *p++ = (i.tm.base_opcode >> 16) & 0xff;
+	    }
+	  else
+	    p = frag_more (2);
 
 	  /* Put out high byte first: can't use md_number_to_chars!  */
 	  *p++ = (i.tm.base_opcode >> 8) & 0xff;
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 0a9cd1c..9851704 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -184,6 +184,7 @@ typedef struct
 #define CpuPadLock    0x40000	/* VIA PadLock required */
 #define CpuSVME	      0x80000	/* AMD Secure Virtual Machine Ext-s required */
 #define CpuVMX	     0x100000	/* VMX Instructions required */
+#define CpuMNI	     0x200000	/* Merom New Instructions required */
 
   /* These flags are set by gas depending on the flag_code.  */
 #define Cpu64	     0x4000000   /* 64bit support required  */
@@ -192,7 +193,7 @@ typedef struct
   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
 	|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
-	|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME)
+	|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI)
 
   /* the bits in opcode_modifier are used to generate the final opcode from
      the base_opcode.  These bits also are used to detect alternate forms of