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| author | Alan Modra <amodra@gmail.com> | 2019-12-12 09:29:45 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2019-12-12 21:58:33 +1030 |
| commit | 4f7cc14110d67a180f5408a91ac53a91f88f776e (patch) | |
| tree | 06f9b92f65556383e9d7cad287ce1b51882c7243 /gas/config/tc-metag.c | |
| parent | 84bc4ba8168154fae0da7d56dcd11df0d4bc44f2 (diff) | |
| download | binutils-4f7cc14110d67a180f5408a91ac53a91f88f776e.zip binutils-4f7cc14110d67a180f5408a91ac53a91f88f776e.tar.gz binutils-4f7cc14110d67a180f5408a91ac53a91f88f776e.tar.bz2 | |
gas signed overflow fixes
* config/tc-aarch64.c (get_aarch64_insn): Avoid signed overflow.
* config/tc-metag.c (parse_dalu): Likewise.
* config/tc-tic4x.c (md_pcrel_from): Likewise.
* config/tc-tic6x.c (tic6x_output_unwinding): Likewise.
* config/tc-csky.c (parse_fexp): Use an unsigned char temp buffer.
Don't use register keyword. Avoid signed overflow and remove now
unneccesary char masks. Formatting.
* config/tc-ia64.c (operand_match): Don't use shifts to sign extend.
* config/tc-mep.c (mep_apply_fix): Likewise.
* config/tc-pru.c (md_apply_fix): Likewise.
* config/tc-riscv.c (load_const): Likewise.
* config/tc-nios2.c (md_apply_fix): Likewise. Don't potentially
truncate fixup before right shift. Tidy BFD_RELOC_NIOS2_HIADJ16
calculation.
Diffstat (limited to 'gas/config/tc-metag.c')
| -rw-r--r-- | gas/config/tc-metag.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gas/config/tc-metag.c b/gas/config/tc-metag.c index c7bb36d..d056e9a 100644 --- a/gas/config/tc-metag.c +++ b/gas/config/tc-metag.c @@ -5340,7 +5340,7 @@ parse_dalu (const char *line, metag_insn *insn, /* Only MOV instructions have a DSP register as a destination. Set the MOV DSPe.r opcode. The simple OR'ing is OK because the usual MOV opcode is 0x00. */ - insn->bits = (0x91 << 24); + insn->bits = 0x91u << 24; du_shift = 0; l1_shift = 2; regs_shift[0] = 19; @@ -5455,7 +5455,7 @@ parse_dalu (const char *line, metag_insn *insn, du_shift = 0; l1_shift = 2; regs_shift[1] = 14; - insn->bits = (0x92 << 24); /* Set opcode. */ + insn->bits = 0x92u << 24; /* Set opcode. */ } } } |