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| author | Jie Zhang <jie.zhang@analog.com> | 2009-09-03 16:17:36 +0000 |
|---|---|---|
| committer | Jie Zhang <jie.zhang@analog.com> | 2009-09-03 16:17:36 +0000 |
| commit | c958a8a8fb341605fa49cb30d62e98f1b833f542 (patch) | |
| tree | 4842b85e37b23a13c68aa40ccaf409f9e10cdd18 /gas/config/bfin-parse.y | |
| parent | 1d3ad4d0b0eafa4c7182f41077b6bfa1d8bc53c8 (diff) | |
| download | binutils-c958a8a8fb341605fa49cb30d62e98f1b833f542.zip binutils-c958a8a8fb341605fa49cb30d62e98f1b833f542.tar.gz binutils-c958a8a8fb341605fa49cb30d62e98f1b833f542.tar.bz2 | |
gas/
* config/bfin-defs.h (IS_GENREG): Define.
(IS_DAGREG): Define.
(IS_SYSREG): Define.
* config/bfin-parse.y (asm_1): Check illegal register move
instructions.
gas/testsuite/
* gas/bfin/expected_move_errors.s,
gas/bfin/expected_move_errors.l: Add "LC1 = I0;".
* gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W".
opcodes/
* bfin-dis.c (IS_DREG): Define.
(IS_PREG): Define.
(IS_AREG): Define.
(IS_GENREG): Define.
(IS_DAGREG): Define.
(IS_SYSREG): Define.
(decode_REGMV_0): Check illegal register move instructions.
Diffstat (limited to 'gas/config/bfin-parse.y')
| -rw-r--r-- | gas/config/bfin-parse.y | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y index 81bfef8..952859e 100644 --- a/gas/config/bfin-parse.y +++ b/gas/config/bfin-parse.y @@ -1720,9 +1720,18 @@ asm_1: | REG ASSIGN REG { - if (IS_ALLREG ($1) && IS_ALLREG ($3)) + if ((IS_GENREG ($1) && IS_GENREG ($3)) + || (IS_GENREG ($1) && IS_DAGREG ($3)) + || (IS_DAGREG ($1) && IS_GENREG ($3)) + || (IS_DAGREG ($1) && IS_DAGREG ($3)) + || (IS_GENREG ($1) && $3.regno == REG_USP) + || ($1.regno == REG_USP && IS_GENREG ($3)) + || (IS_DREG ($1) && IS_SYSREG ($3)) + || (IS_PREG ($1) && IS_SYSREG ($3)) + || (IS_SYSREG ($1) && IS_DREG ($3)) + || (IS_SYSREG ($1) && IS_PREG ($3)) + || (IS_SYSREG ($1) && $3.regno == REG_USP)) { - notethat ("REGMV: allregs = allregs\n"); $$ = bfin_gen_regmv (&$3, &$1); } else |