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authorXiao Zeng <zengxiao@eswincomputing.com>2024-06-06 15:59:51 +0800
committerNelson Chu <nelson@rivosinc.com>2024-06-06 16:10:48 +0800
commitaf38c6367ff0c6af1639b389eb34cf9983c30ff5 (patch)
tree7669d1eabbe02ea5befdadbc0c3cee1666c83dd8 /gas/NEWS
parent42878336131e1b90623c5e2d7d011acc9b35c950 (diff)
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RISC-V: Add support for Zfbfmin extension
This implements the Zfbfmin extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts> 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and FMV.H.X instructions as defined in the Zfh extension. 2 The Zfhmin extension includes the following instructions from the Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc> 3 Zfhmin extension depend on 'F'. 4 Simply put, just make Zfbfmin dependent on Zfhmin. Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and FMV.H.X instructions an independent extension to achieve precise dependency relationships for the Zfbfmin. 5 For relevant information in gcc, please refer to: <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zfbfmin.d: New test. * testsuite/gas/riscv/zfbfmin.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define. (MASK_FCVT_BF16_S): Ditto. (MATCH_FCVT_S_BF16): Ditto. (MASK_FCVT_S_BF16): Ditto. (DECLARE_INSN): New declarations for Zfbfmin. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN. opcodes/ChangeLog: * riscv-opc.c: Add Zfbfmin instructions.
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diff --git a/gas/NEWS b/gas/NEWS
index e51c3bb..cdf3094 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -21,6 +21,8 @@
* Add support for RISC-V Zcmp extension with version 1.0.
+* Add support for RISC-V Zfbfmin extension with version 1.0.
+
* The base register operand in D(X,B) and D(L,B) may be explicitly omitted
in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
D(X,%r0), D(L,0), and D(L,%r0).