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| author | Stafford Horne <shorne@gmail.com> | 2019-06-13 06:16:19 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2019-06-13 06:16:19 +0900 |
| commit | eb212c84a12bd0adb29792737ab2423d72c182f7 (patch) | |
| tree | 136970d03fc81f3eb9dc2d4bb6a942466f1ba29e /cpu/or1k.cpu | |
| parent | d3ad6278d6b977cfeb3156b65862224899549c76 (diff) | |
| download | binutils-eb212c84a12bd0adb29792737ab2423d72c182f7.zip binutils-eb212c84a12bd0adb29792737ab2423d72c182f7.tar.gz binutils-eb212c84a12bd0adb29792737ab2423d72c182f7.tar.bz2 | |
cpu/or1k: Document no branch delay slot architectures and l.adrp
The 'nd' architectures did not mention what the 'nd' stands for.
Document that these mean 'no brach delay slot'.
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
(l-adrp): Improve comment.
Diffstat (limited to 'cpu/or1k.cpu')
| -rw-r--r-- | cpu/or1k.cpu | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu index e1ae1b8..b796862 100644 --- a/cpu/or1k.cpu +++ b/cpu/or1k.cpu @@ -77,7 +77,7 @@ (define-mach (name or32nd) - (comment "Generic OpenRISC 1000 32-bit CPU") + (comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot") (cpu or1k32bf) (bfd-name "or1knd") ) @@ -92,7 +92,7 @@ ; OpenRISC 1200 - 32-bit or1k CPU implementation (define-model - (name or1200nd) (comment "OpenRISC 1200 model") + (name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot") (attrs NO-DELAY-SLOT) (mach or32nd) (unit u-exec "Execution Unit" () 1 1 () () () ()) @@ -120,7 +120,7 @@ (define-mach (name or64nd) - (comment "Generic OpenRISC 1000 ND 64-bit CPU") + (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot") (cpu or1k64bf) (bfd-name "or1k64nd") ) |