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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-02 11:53:30 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-02 11:58:44 +0100 |
| commit | a4ddc54ec1cd187c844ca631fe0315bf1d78e96f (patch) | |
| tree | d13d98c24eb7b60d6203e0adb8bc6edf50b9519c /binutils/ChangeLog | |
| parent | 39ff1b79f687b65f4144ddb379f22587003443fb (diff) | |
| download | binutils-a4ddc54ec1cd187c844ca631fe0315bf1d78e96f.zip binutils-a4ddc54ec1cd187c844ca631fe0315bf1d78e96f.tar.gz binutils-a4ddc54ec1cd187c844ca631fe0315bf1d78e96f.tar.bz2 | |
MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassembly
Correct the disassembly of the PC-relative immediate argument of the
MIPS16 synthetic LA, LW, DLA and LD instructions and do not mask the
LSB, which in this case is a part of the data address rather than the
ISA bit and has to be fully presented.
opcodes/
* mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
and branches and not synthetic data instructions.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the
disassembly of PC-relative LA and LW synthetic instructions.
Diffstat (limited to 'binutils/ChangeLog')
| -rw-r--r-- | binutils/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 5fdcd4d..aef436d 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2017-05-02 Maciej W. Rozycki <macro@imgtec.com> + + * testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the + disassembly of PC-relative LA and LW synthetic instructions. + 2017-05-02 Nick Clifton <nickc@redhat.com> PR 21440 |