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authorChristoph Müllner <christoph.muellner@vrull.eu>2022-06-28 17:42:58 +0200
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>2022-09-22 18:06:09 +0200
commitfb1737381d886c7c0a4e870af078c473ac463fce (patch)
treef3b4d2a86f1085607c18b2554e85749a2627538d /bfd
parentaaf3f3f3bb38a59125ea34afa0ef7e0e14c2e916 (diff)
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RISC-V: Add generic support for vendor extensions
This patch introduces changes that allow the integration of vendor ISA extensions: * Define a list of vendor extensions (riscv_supported_vendor_x_ext) where vendor extensions can be added * Introduce a section with a table in the documentation where vendor extensions can be added To add a vendor extension that consists of instructions only, the following things need to be done: * Add the extension to the riscv_supported_vendor_x_ext list * Add lookup entry in riscv_multi_subset_supports * Documenting the extension in c-riscv.texti * Add test cases for all instructions * Add MATCH*/MASK* constants and DECLARE_INSN() for all instructions * Add new instruction class to enum riscv_insn_class * Define the instructions in riscv_opcodes * Additional changes if necessary (depending on the instructions) Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'bfd')
-rw-r--r--bfd/elfxx-riscv.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 7eda177..cb3a980 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1222,12 +1222,18 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
{NULL, 0, 0, 0, 0}
};
+static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
+{
+ {NULL, 0, 0, 0, 0}
+};
+
const struct riscv_supported_ext *riscv_all_supported_ext[] =
{
riscv_supported_std_ext,
riscv_supported_std_z_ext,
riscv_supported_std_s_ext,
riscv_supported_std_zxm_ext,
+ riscv_supported_vendor_x_ext,
NULL
};
@@ -1483,8 +1489,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec,
case RV_ISA_CLASS_ZXM: table = riscv_supported_std_zxm_ext; break;
case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break;
case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
- case RV_ISA_CLASS_X:
- break;
+ case RV_ISA_CLASS_X: table = riscv_supported_vendor_x_ext; break;
default:
table = riscv_supported_std_ext;
}