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| author | Vineet Gupta <vineetg@rivosinc.com> | 2021-12-20 18:34:13 -0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-12-24 15:17:52 +0800 |
| commit | a63375ac337903d4394b2d88788353d06cf7a086 (patch) | |
| tree | 30b22f80ca8d3441085115169e27be536f8d63d7 /bfd | |
| parent | 5c3ffbc4dd9454c56598e28a25d8d0c0faf1e8bc (diff) | |
| download | binutils-a63375ac337903d4394b2d88788353d06cf7a086.zip binutils-a63375ac337903d4394b2d88788353d06cf7a086.tar.gz binutils-a63375ac337903d4394b2d88788353d06cf7a086.tar.bz2 | |
RISC-V: Hypervisor ext: support Privileged Spec 1.12
This is the Hypervisor Extension 1.0
- Hypervisor Memory-Management Instructions
HFENCE.VVMA, HFENCE.GVMA,
- Hypervisor Virtual Machine Load and Store Instructions
HLV.B, HLV.BU, HSV.B,
HLV.H, HLV.HU, HLVX.HU, HSB.H,
HLV.W, HLV.WU, HLVX.WU, HSV.W,
HLV.D, HSV.D
- Hypervisor CSRs (some new, some address changed)
hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip,
htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah,
vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp,
Note that following were added already as part of svinval extension
support:
HINVAL.GVMA, HINVAL.VVMA
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>
bfd/
* cpu-riscv.c (riscv_priv_specs): Added entry for 1.12.
* cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12.
gas/
* config/tc-riscv.c (abort_version): Updated comment.
(validate_riscv_insn): Annotate switch-break.
* testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor.
* testsuite/gas/riscv/h-ext-32.s: Likewise.
* testsuite/gas/riscv/h-ext-64.d: Likewise.
* testsuite/gas/riscv/h-ext-64.s: Likewise.
include/
* opcode/riscv-opc.h: Added encodings for hypervisor csrs and
instrcutions.
opcodes/
* riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/cpu-riscv.c | 1 | ||||
| -rw-r--r-- | bfd/cpu-riscv.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c index 813f2c3..5038029 100644 --- a/bfd/cpu-riscv.c +++ b/bfd/cpu-riscv.c @@ -117,6 +117,7 @@ const struct riscv_spec riscv_priv_specs[] = {"1.9.1", PRIV_SPEC_CLASS_1P9P1}, {"1.10", PRIV_SPEC_CLASS_1P10}, {"1.11", PRIV_SPEC_CLASS_1P11}, + {"1.12", PRIV_SPEC_CLASS_1P12}, }; /* Get the corresponding CSR version class by giving privilege diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h index ed5ee7e..b251d63 100644 --- a/bfd/cpu-riscv.h +++ b/bfd/cpu-riscv.h @@ -32,6 +32,7 @@ enum riscv_spec_class PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P11, + PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT, }; |