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| author | Dongyan Chen <chendongyan@isrc.iscas.ac.cn> | 2024-11-28 20:35:36 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-12-02 10:13:11 +0800 |
| commit | 69a91bcd6eb72ccf5144bbcdee624c481066e5b3 (patch) | |
| tree | 534b5258293415313c70349cf21e0e9b54ec7019 /bfd | |
| parent | 4c35cbf9e1d1e26a470f7a12fb005725e5d8e9fe (diff) | |
| download | binutils-69a91bcd6eb72ccf5144bbcdee624c481066e5b3.zip binutils-69a91bcd6eb72ccf5144bbcdee624c481066e5b3.tar.gz binutils-69a91bcd6eb72ccf5144bbcdee624c481066e5b3.tar.bz2 | |
RISC-V: Add support for ssdbltrp and smdbltrp extension.
This implements the ssdbltrp extensons, version 1.0[1] and the smdbltrp
extensions, version1.0[2].
[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc
[2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc
bfd/ChangeLog:
* elfxx-riscv.c: Add 'ssdbltrp' and 'smdbltrp' to the list of konwn
standard extensions.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/imply.d: Ditto.
* testsuite/gas/riscv/imply.s: Ditto.
* testsuite/gas/riscv/march-help.l: Ditto.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 45da83e..a6511f6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1262,6 +1262,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"smcntrpmf", "+zicsr", check_implicit_always}, {"smstateen", "+ssstateen", check_implicit_always}, {"smepmp", "+zicsr", check_implicit_always}, + {"smdbltrp", "+zicsr", check_implicit_always}, {"ssaia", "+zicsr", check_implicit_always}, {"sscsrind", "+zicsr", check_implicit_always}, @@ -1272,6 +1273,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"sstvala", "+zicsr", check_implicit_always}, {"sstvecd", "+zicsr", check_implicit_always}, {"ssu64xl", "+zicsr", check_implicit_always}, + {"ssdbltrp", "+zicsr", check_implicit_always}, {"svade", "+zicsr", check_implicit_always}, {"svadu", "+zicsr", check_implicit_always}, @@ -1448,6 +1450,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smrnmi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"smdbltrp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1458,6 +1461,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssdbltrp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, |