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author | Will Schmidt <will_schmidt@vnet.ibm.com> | 2021-04-12 14:11:02 -0500 |
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committer | Will Schmidt <will_schmidt@vnet.ibm.com> | 2021-04-12 14:11:02 -0500 |
commit | c8a379440e0f8bf94ed5730e823c9256e64bf37c (patch) | |
tree | 60c862aedcb629281ae30b2598d1ace1156ab9e6 /bfd/cpu-mips.c | |
parent | e3d528d7e6a6b863d30aaecf74adf8c78286f84c (diff) | |
download | binutils-c8a379440e0f8bf94ed5730e823c9256e64bf37c.zip binutils-c8a379440e0f8bf94ed5730e823c9256e64bf37c.tar.gz binutils-c8a379440e0f8bf94ed5730e823c9256e64bf37c.tar.bz2 |
[PATCH] gdb-power10-single-step
Hi,
This is based on a patch originally written by Alan Modra.
Powerpc / Power10 ISA 3.1 adds prefixed instructions, which
are 8 bytes in length. This is in contrast to powerpc previously
always having 4 byte instruction length. This patch implements
changes to allow GDB to better detect prefixed instructions, and
handle single stepping across the 8 byte instructions.
Added #defines to help test for PNOP and prefix instructions.
Update ppc_displaced_step_copy_insn() to handle pnop and prefixed
instructions whem R=0 (non-pc-relative).
Updated ppc_displaced_step_fixup() to properly handle the offset
value matching the current instruction size
Updated the for-loop within ppc_deal_with_atomic_sequence() to
count instructions properly in case we have a mix of 4-byte and
8-byte instructions within the atomic_sequence_length.
Added testcase and harness to exercise pc-relative load/store
instructions with R=0.
2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com>
gdb/ChangeLog:
* rs6000-tdep.c: Add support for single-stepping of
prefixed instructions.
gdb/testsuite/ChangeLog:
* gdb.arch/powerpc-plxv-nonrel.s: Testcase using
non-relative plxv instructions.
* gdb.arch/powerpc-plxv-nonrel.exp: Testcase harness.
Diffstat (limited to 'bfd/cpu-mips.c')
0 files changed, 0 insertions, 0 deletions