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authorLuis Machado <luis.machado@linaro.org>2020-05-15 23:06:52 -0300
committerLuis Machado <luis.machado@linaro.org>2020-05-27 09:41:53 -0300
commitf8c6d1528c19b11fdaa3ec949147280e500446e2 (patch)
tree9f4f5c85741aca8fe82f881e49e351d434c7344a
parentc2b750436a9db8cf491ddeb316bc71e4b65110b6 (diff)
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Fix PR 26000, logical bitwise error / prologue analyzer
This fixes an instruction mask typo. We should be matching only ldrd (immediate) and not any other of its variants. As is, it never matches anything. With the patch, the instruction mask also allows matching of ldrd (literal), but the check for SP discards this particular instruction pattern, as it has a hardcoded PC register. gdb/ChangeLog: 2020-05-27 Luis Machado <luis.machado@linaro.org> PR tdep/26000 * arm-tdep.c (thumb_analyze_prologue): Fix instruction matching for ldrd (immediate).
-rw-r--r--gdb/ChangeLog6
-rw-r--r--gdb/arm-tdep.c2
2 files changed, 7 insertions, 1 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index b0ec14f..6cadd33 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,9 @@
+2020-05-27 Luis Machado <luis.machado@linaro.org>
+
+ PR tdep/26000
+ * arm-tdep.c (thumb_analyze_prologue): Fix instruction matching
+ for ldrd (immediate).
+
2020-05-26 Philippe Waroquiers <philippe.waroquiers@skynet.be>
* command.h: Add comment giving the name of class_tui.
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 3e08524..5c5efe5 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -931,7 +931,7 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
parameters from memory. */
;
- else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2,
+ else if ((insn & 0xff70) == 0xe950 /* ldrd Rt, Rt2,
[Rn, #+/-imm] */
&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
/* Similarly ignore dual loads from the stack. */