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author | Jan Beulich <jbeulich@suse.com> | 2020-07-14 10:23:36 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2020-07-14 10:23:36 +0200 |
commit | e8b5d5f9713b7c74f95c4ff573ddeb7ebdb3fbc3 (patch) | |
tree | 0bafc00c1efb11d44eefb9020b4362bc2b028853 | |
parent | 38397794c90dc92e92ca4b0a9d00005f23fe500b (diff) | |
download | binutils-e8b5d5f9713b7c74f95c4ff573ddeb7ebdb3fbc3.zip binutils-e8b5d5f9713b7c74f95c4ff573ddeb7ebdb3fbc3.tar.gz binutils-e8b5d5f9713b7c74f95c4ff573ddeb7ebdb3fbc3.tar.bz2 |
x86: drop dead code from OP_IMREG()
There's only a very limited set of modes that this function gets invoked
with - avoid it being more generic than it needs to be. This may, down
the road, allow actually doing away with the function altogether.
This eliminates a first improperly used "USED_REX (0)".
-rw-r--r-- | gas/ChangeLog | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-pseudos.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-pseudos.s | 2 | ||||
-rw-r--r-- | opcodes/ChangeLog | 8 | ||||
-rw-r--r-- | opcodes/i386-dis.c | 46 |
5 files changed, 24 insertions, 40 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 88dffa5..ba55ed9 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2020-07-14 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/i386/x86-64-pseudos.s: Add empty-REX tests for + not-ModR/M-encoded byte register cases. + * testsuite/gas/i386/x86-64-pseudos.d: Adjust expectations. + +2020-07-14 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/i386/ilp32/x86-64-arch-1.d, testsuite/gas/i386/ilp32/x86-64-arch-2.d, testsuite/gas/i386/ilp32/x86-64-avx-intel.d, diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d index 529578b..26944b9 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.d +++ b/gas/testsuite/gas/i386/x86-64-pseudos.d @@ -301,6 +301,8 @@ Disassembly of section .text: +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%rax\),%xmm2 +[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%rax\),%xmm2 +[a-f0-9]+: 88 c4 mov %al,%ah + +[a-f0-9]+: 40 d3 e0 rex shl %cl,%eax + +[a-f0-9]+: 40 a0 01 00 00 00 00 00 00 00 rex movabs 0x1,%al +[a-f0-9]+: 40 89 c3 rex mov %eax,%ebx +[a-f0-9]+: 41 89 c6 mov %eax,%r14d +[a-f0-9]+: 41 89 00 mov %eax,\(%r8\) diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index 3bda573..0529075 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -305,6 +305,8 @@ _start: {disp8} movaps 128(%rax),%xmm2 {disp32} movaps 128(%rax),%xmm2 {rex} mov %al,%ah + {rex} shl %cl, %eax + {rex} movabs 1, %al {rex} movl %eax,%ebx {rex} movl %eax,%r14d {rex} movl %eax,(%r8) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 83dfd2e..26b56ba 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2020-07-14 Jan Beulich <jbeulich@suse.com> + + * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH, + CH, DH, BH, AX, DX): Delete. + (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg, + eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg, + dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left. + 2020-07-10 Lili Cui <lili.cui@intel.com> * i386-dis.c (TMM): New. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 6a14f9e..b635a04 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -326,23 +326,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define RMDX { OP_REG, dx_reg } #define eAX { OP_IMREG, eAX_reg } -#define eBX { OP_IMREG, eBX_reg } -#define eCX { OP_IMREG, eCX_reg } -#define eDX { OP_IMREG, eDX_reg } -#define eSP { OP_IMREG, eSP_reg } -#define eBP { OP_IMREG, eBP_reg } -#define eSI { OP_IMREG, eSI_reg } -#define eDI { OP_IMREG, eDI_reg } #define AL { OP_IMREG, al_reg } #define CL { OP_IMREG, cl_reg } -#define DL { OP_IMREG, dl_reg } -#define BL { OP_IMREG, bl_reg } -#define AH { OP_IMREG, ah_reg } -#define CH { OP_IMREG, ch_reg } -#define DH { OP_IMREG, dh_reg } -#define BH { OP_IMREG, bh_reg } -#define AX { OP_IMREG, ax_reg } -#define DX { OP_IMREG, dx_reg } #define zAX { OP_IMREG, z_mode_ax_reg } #define indirDX { OP_IMREG, indir_dx_reg } @@ -15285,36 +15270,17 @@ OP_IMREG (int code, int sizeflag) else s = "(%dx)"; break; - case ax_reg: case cx_reg: case dx_reg: case bx_reg: - case sp_reg: case bp_reg: case si_reg: case di_reg: - s = names16[code - ax_reg]; - break; - case es_reg: case ss_reg: case cs_reg: - case ds_reg: case fs_reg: case gs_reg: - s = names_seg[code - es_reg]; - break; - case al_reg: case ah_reg: case cl_reg: case ch_reg: - case dl_reg: case dh_reg: case bl_reg: case bh_reg: - USED_REX (0); - if (rex) - s = names8rex[code - al_reg]; - else - s = names8[code - al_reg]; + case al_reg: case cl_reg: + s = names8[code - al_reg]; break; - case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: - case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: + case eAX_reg: USED_REX (REX_W); if (rex & REX_W) - s = names64[code - eAX_reg]; - else { - if (sizeflag & DFLAG) - s = names32[code - eAX_reg]; - else - s = names16[code - eAX_reg]; - used_prefixes |= (prefixes & PREFIX_DATA); + s = *names64; + break; } - break; + /* Fall through. */ case z_mode_ax_reg: if ((rex & REX_W) || (sizeflag & DFLAG)) s = *names32; |