diff options
author | John Baldwin <jhb@FreeBSD.org> | 2019-03-12 13:39:02 -0700 |
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committer | John Baldwin <jhb@FreeBSD.org> | 2019-03-12 13:45:23 -0700 |
commit | dd6876c91cd40cc105b1a91f418ca2c80683b314 (patch) | |
tree | 394033e0658212a6461dd32784d158ff1d16f6e6 | |
parent | 1163a4b7a38a79ebd153dc5ee76ce93877d21dbd (diff) | |
download | binutils-dd6876c91cd40cc105b1a91f418ca2c80683b314.zip binutils-dd6876c91cd40cc105b1a91f418ca2c80683b314.tar.gz binutils-dd6876c91cd40cc105b1a91f418ca2c80683b314.tar.bz2 |
Support fs_base and gs_base on FreeBSD/i386.
The i386 BSD native target uses the same ptrace operations
(PT_[GS]ET[FG]SBASE) as the amd64 BSD native target to fetch and store
the registers.
The amd64 BSD native now uses 'tdep->fsbase_regnum' instead of
hardcoding AMD64_FSBASE_REGNUM and AMD64_GSBASE_REGNUM to support
32-bit targets. In addition, the store operations explicitly zero the
new register value before fetching it from the register cache to
ensure 32-bit values are zero-extended.
gdb/ChangeLog:
* amd64-bsd-nat.c (amd64bsd_fetch_inferior_registers): Use
tdep->fsbase_regnum instead of constants for fs_base and gs_base.
(amd64bsd_store_inferior_registers): Likewise.
* amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description):
Enable segment base registers.
* i386-bsd-nat.c (i386bsd_fetch_inferior_registers): Use
PT_GETFSBASE and PT_GETGSBASE.
(i386bsd_store_inferior_registers): Use PT_SETFSBASE and
PT_SETGSBASE.
* i386-fbsd-nat.c (i386_fbsd_nat_target::read_description): Enable
segment base registers.
* i386-fbsd-tdep.c (i386fbsd_core_read_description): Likewise.
-rw-r--r-- | gdb/ChangeLog | 15 | ||||
-rw-r--r-- | gdb/amd64-bsd-nat.c | 26 | ||||
-rw-r--r-- | gdb/amd64-fbsd-nat.c | 4 | ||||
-rw-r--r-- | gdb/i386-bsd-nat.c | 54 | ||||
-rw-r--r-- | gdb/i386-fbsd-nat.c | 2 | ||||
-rw-r--r-- | gdb/i386-fbsd-tdep.c | 2 |
6 files changed, 91 insertions, 12 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 79ba941..c91e975 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,5 +1,20 @@ 2019-03-12 John Baldwin <jhb@FreeBSD.org> + * amd64-bsd-nat.c (amd64bsd_fetch_inferior_registers): Use + tdep->fsbase_regnum instead of constants for fs_base and gs_base. + (amd64bsd_store_inferior_registers): Likewise. + * amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description): + Enable segment base registers. + * i386-bsd-nat.c (i386bsd_fetch_inferior_registers): Use + PT_GETFSBASE and PT_GETGSBASE. + (i386bsd_store_inferior_registers): Use PT_SETFSBASE and + PT_SETGSBASE. + * i386-fbsd-nat.c (i386_fbsd_nat_target::read_description): Enable + segment base registers. + * i386-fbsd-tdep.c (i386fbsd_core_read_description): Likewise. + +2019-03-12 John Baldwin <jhb@FreeBSD.org> + * amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description): Update calls to i386_target_description to add 'segments' parameter. diff --git a/gdb/amd64-bsd-nat.c b/gdb/amd64-bsd-nat.c index a2a91ab..35763a5 100644 --- a/gdb/amd64-bsd-nat.c +++ b/gdb/amd64-bsd-nat.c @@ -43,6 +43,9 @@ amd64bsd_fetch_inferior_registers (struct regcache *regcache, int regnum) { struct gdbarch *gdbarch = regcache->arch (); pid_t pid = get_ptrace_pid (regcache->ptid ()); +#if defined(PT_GETFSBASE) || defined(PT_GETGSBASE) + const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); +#endif if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum)) { @@ -57,27 +60,27 @@ amd64bsd_fetch_inferior_registers (struct regcache *regcache, int regnum) } #ifdef PT_GETFSBASE - if (regnum == -1 || regnum == AMD64_FSBASE_REGNUM) + if (regnum == -1 || regnum == tdep->fsbase_regnum) { register_t base; if (ptrace (PT_GETFSBASE, pid, (PTRACE_TYPE_ARG3) &base, 0) == -1) perror_with_name (_("Couldn't get segment register fs_base")); - regcache->raw_supply (AMD64_FSBASE_REGNUM, &base); + regcache->raw_supply (tdep->fsbase_regnum, &base); if (regnum != -1) return; } #endif #ifdef PT_GETGSBASE - if (regnum == -1 || regnum == AMD64_GSBASE_REGNUM) + if (regnum == -1 || regnum == tdep->fsbase_regnum + 1) { register_t base; if (ptrace (PT_GETGSBASE, pid, (PTRACE_TYPE_ARG3) &base, 0) == -1) perror_with_name (_("Couldn't get segment register gs_base")); - regcache->raw_supply (AMD64_GSBASE_REGNUM, &base); + regcache->raw_supply (tdep->fsbase_regnum + 1, &base); if (regnum != -1) return; } @@ -116,6 +119,9 @@ amd64bsd_store_inferior_registers (struct regcache *regcache, int regnum) { struct gdbarch *gdbarch = regcache->arch (); pid_t pid = get_ptrace_pid (regcache->ptid ()); +#if defined(PT_SETFSBASE) || defined(PT_SETGSBASE) + const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); +#endif if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum)) { @@ -134,11 +140,13 @@ amd64bsd_store_inferior_registers (struct regcache *regcache, int regnum) } #ifdef PT_SETFSBASE - if (regnum == -1 || regnum == AMD64_FSBASE_REGNUM) + if (regnum == -1 || regnum == tdep->fsbase_regnum) { register_t base; - regcache->raw_collect (AMD64_FSBASE_REGNUM, &base); + /* Clear the full base value to support 32-bit targets. */ + base = 0; + regcache->raw_collect (tdep->fsbase_regnum, &base); if (ptrace (PT_SETFSBASE, pid, (PTRACE_TYPE_ARG3) &base, 0) == -1) perror_with_name (_("Couldn't write segment register fs_base")); @@ -147,11 +155,13 @@ amd64bsd_store_inferior_registers (struct regcache *regcache, int regnum) } #endif #ifdef PT_SETGSBASE - if (regnum == -1 || regnum == AMD64_GSBASE_REGNUM) + if (regnum == -1 || regnum == tdep->fsbase_regnum + 1) { register_t base; - regcache->raw_collect (AMD64_GSBASE_REGNUM, &base); + /* Clear the full base value to support 32-bit targets. */ + base = 0; + regcache->raw_collect (tdep->fsbase_regnum + 1, &base); if (ptrace (PT_SETGSBASE, pid, (PTRACE_TYPE_ARG3) &base, 0) == -1) perror_with_name (_("Couldn't write segment register gs_base")); diff --git a/gdb/amd64-fbsd-nat.c b/gdb/amd64-fbsd-nat.c index 9fff763..cc676d3 100644 --- a/gdb/amd64-fbsd-nat.c +++ b/gdb/amd64-fbsd-nat.c @@ -190,13 +190,13 @@ amd64_fbsd_nat_target::read_description () if (is64) return amd64_target_description (xcr0, true); else - return i386_target_description (xcr0, false); + return i386_target_description (xcr0, true); } #endif if (is64) return amd64_target_description (X86_XSTATE_SSE_MASK, true); else - return i386_target_description (X86_XSTATE_SSE_MASK, false); + return i386_target_description (X86_XSTATE_SSE_MASK, true); } #if defined(HAVE_PT_GETDBREGS) && defined(USE_SIGTRAP_SIGINFO) diff --git a/gdb/i386-bsd-nat.c b/gdb/i386-bsd-nat.c index 009a8dc..a10b496 100644 --- a/gdb/i386-bsd-nat.c +++ b/gdb/i386-bsd-nat.c @@ -144,6 +144,33 @@ i386bsd_fetch_inferior_registers (struct regcache *regcache, int regnum) return; } +#ifdef PT_GETFSBASE + if (regnum == -1 || regnum == I386_FSBASE_REGNUM) + { + register_t base; + + if (ptrace (PT_GETFSBASE, pid, (PTRACE_TYPE_ARG3) &base, 0) == -1) + perror_with_name (_("Couldn't get segment register fs_base")); + + regcache->raw_supply (I386_FSBASE_REGNUM, &base); + if (regnum != -1) + return; + } +#endif +#ifdef PT_GETGSBASE + if (regnum == -1 || regnum == I386_GSBASE_REGNUM) + { + register_t base; + + if (ptrace (PT_GETGSBASE, pid, (PTRACE_TYPE_ARG3) &base, 0) == -1) + perror_with_name (_("Couldn't get segment register gs_base")); + + regcache->raw_supply (I386_GSBASE_REGNUM, &base); + if (regnum != -1) + return; + } +#endif + if (regnum == -1 || regnum >= I386_ST0_REGNUM) { struct fpreg fpregs; @@ -211,6 +238,33 @@ i386bsd_store_inferior_registers (struct regcache *regcache, int regnum) return; } +#ifdef PT_SETFSBASE + if (regnum == -1 || regnum == I386_FSBASE_REGNUM) + { + register_t base; + + regcache->raw_collect (I386_FSBASE_REGNUM, &base); + + if (ptrace (PT_SETFSBASE, pid, (PTRACE_TYPE_ARG3) &base, 0) == -1) + perror_with_name (_("Couldn't write segment register fs_base")); + if (regnum != -1) + return; + } +#endif +#ifdef PT_SETGSBASE + if (regnum == -1 || regnum == I386_GSBASE_REGNUM) + { + register_t base; + + regcache->raw_collect (I386_GSBASE_REGNUM, &base); + + if (ptrace (PT_SETGSBASE, pid, (PTRACE_TYPE_ARG3) &base, 0) == -1) + perror_with_name (_("Couldn't write segment register gs_base")); + if (regnum != -1) + return; + } +#endif + if (regnum == -1 || regnum >= I386_ST0_REGNUM) { struct fpreg fpregs; diff --git a/gdb/i386-fbsd-nat.c b/gdb/i386-fbsd-nat.c index 7106e90..be5d4c6 100644 --- a/gdb/i386-fbsd-nat.c +++ b/gdb/i386-fbsd-nat.c @@ -160,7 +160,7 @@ i386_fbsd_nat_target::read_description () if (x86bsd_xsave_len == 0) xcr0 = X86_XSTATE_SSE_MASK; - return i386_target_description (xcr0, false); + return i386_target_description (xcr0, true); } #endif diff --git a/gdb/i386-fbsd-tdep.c b/gdb/i386-fbsd-tdep.c index 2f28bad..ac57e73 100644 --- a/gdb/i386-fbsd-tdep.c +++ b/gdb/i386-fbsd-tdep.c @@ -267,7 +267,7 @@ i386fbsd_core_read_description (struct gdbarch *gdbarch, struct target_ops *target, bfd *abfd) { - return i386_target_description (i386fbsd_core_read_xcr0 (abfd), false); + return i386_target_description (i386fbsd_core_read_xcr0 (abfd), true); } /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |