aarch64: Add support for FEAT_SVE_B16B16 feature.

In the current code, SVE2 Bfloat16 instructions are implemented with tick
FEAT_B16B16 and command line flag "+b16b16" and this feature was suspended
due to incomplete support.

In the new spec available here[1], FEAT_B16B16 is replaced with
FEAT_SVE_B16B16 and command line flag "+b16b16" is replace with "sve-b16b16".

Also the test files related to FEAT_SVE_B16B16 are prefixed with sve-b16b16*.
eg: sve-b16b16-sve2-1.s, sve-b16b16-sve2-1.d.

This patch supports the SVE Z-targeting non-widening BFloat16 instructions
with command line flag "+sve-b16b16+sve2".
[1]: https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions?lang=en

16 files changed, 39 insertions, 149 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index d2ebe3f..b019ea3 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10740,9 +10740,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"rasv2",		AARCH64_FEATURE (RASv2), AARCH64_FEATURE (RAS)},
   {"ite",		AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
   {"d128",		AARCH64_FEATURE (D128), D128_FEATURE_DEPS},
-  // Feature b16b16 is currently incomplete.
-  // TODO: finish implementation and enable relevant flags.
-  //{"b16b16",		AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
+  {"sve-b16b16",	AARCH64_FEATURE (SVE_B16B16), AARCH64_NO_FEATURES},
   {"sme2p1",		AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
   {"sve2p1",		AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
   {"rcpc3",		AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 282fae2..fc14e51 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -161,8 +161,6 @@ automatically cause those extensions to be disabled.
 @headitem Extension @tab Depends upon @tab Description
 @item @code{aes} @tab @code{simd}
  @tab Enable the AES and PMULL cryptographic extensions.
-@c @item @code{b16b16} @tab @code{sve2}
-@c  @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2.
 @item @code{bf16} @tab @code{fp}
  @tab Enable BFloat16 extension.
 @item @code{brbe} @tab
@@ -295,6 +293,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the Streaming SVE FP8 FMA instructions.  These can also be enabled using @code{+fp8fma+sme2}.
 @item @code{sve} @tab @code{fcma}
  @tab Enable the Scalable Vector Extension.
+@item @code{sve-b16b16} @tab
+@tab Enable the SVE B16B16 extension.  These instructions also require either @code{+sve2} or @code{+sme2}.
 @item @code{sve2} @tab @code{sve}
  @tab Enable SVE2.
 @item @code{sve2-aes} @tab @code{sve2}, @code{aes}
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d
deleted file mode 100644
index 531a597..0000000
--- a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#name: Negative test with missing +b16b16 flag.
-#as: -march=armv9.4-a
-#source: bfloat16-1-invalid.s
-#error_output: bfloat16-1-invalid.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
deleted file mode 100644
index 1e1b701..0000000
--- a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
+++ /dev/null
@@ -1,5 +0,0 @@
-#name: Test Bfloat16 instructions with wrong operand combinations
-#as: -march=armv9.4-a+b16b16
-#source: bfloat16-2-invalid.s
-#error_output: bfloat16-2-invalid.l
-#xfail: *-*-*
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.d b/gas/testsuite/gas/aarch64/bfloat16-bad.d
deleted file mode 100644
index 10d2b00..0000000
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#name: Negative test of Bfloat16 instructions.
-#as: -march=armv9.4-a
-#source: bfloat16-1.s
-#error_output: bfloat16-bad.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.l b/gas/testsuite/gas/aarch64/bfloat16-bad.l
deleted file mode 100644
index d4098bf..0000000
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.l
+++ /dev/null
@@ -1,100 +0,0 @@
-.*: Assembler messages:
-.*: Error: selected processor does not support `bfadd z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfadd z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfadd z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfadd z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfadd z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfadd z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmax z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmax z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmax z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmax z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmax z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmax z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmaxnm z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmaxnm z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmaxnm z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmaxnm z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmaxnm z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmaxnm z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmin z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmin z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmin z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmin z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmin z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmin z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfminnm z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfminnm z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfminnm z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfminnm z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfminnm z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfminnm z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfadd z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfadd z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfadd z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfadd z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfadd z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfadd z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfclamp z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfclamp z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfclamp z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfclamp z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfclamp z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfclamp z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfmla .*
-.*: Error: selected processor does not support `bfmla .*
-.*: Error: selected processor does not support `bfmla .*
-.*: Error: selected processor does not support `bfmla .*
-.*: Error: selected processor does not support `bfmla .*
-.*: Error: selected processor does not support `bfmla .*
-.*: Error: selected processor does not support `bfmla z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmla z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmla z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmla z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmla z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmla z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfmls .*
-.*: Error: selected processor does not support `bfmls .*
-.*: Error: selected processor does not support `bfmls .*
-.*: Error: selected processor does not support `bfmls .*
-.*: Error: selected processor does not support `bfmls .*
-.*: Error: selected processor does not support `bfmls .*
-.*: Error: selected processor does not support `bfmls z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmls z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmls z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmls z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmls z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmls z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfmul z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmul z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmul z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmul z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmul z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmul z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfmul z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfmul z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfmul z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfmul z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfmul z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfmul z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfmul z0.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmul z1.h,z8.h,z5.h\[6\]'
-.*: Error: selected processor does not support `bfmul z2.h,z14.h,z4.h\[4\]'
-.*: Error: selected processor does not support `bfmul z4.h,z21.h,z2.h\[2\]'
-.*: Error: selected processor does not support `bfmul z8.h,z12.h,z1.h\[1\]'
-.*: Error: selected processor does not support `bfmul z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfsub z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfsub z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfsub z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfsub z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfsub z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfsub z16.h,p7\/m,z16.h,z0.h'
-.*: Error: selected processor does not support `bfsub z0.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfsub z1.h,z8.h,z8.h'
-.*: Error: selected processor does not support `bfsub z2.h,z12.h,z4.h'
-.*: Error: selected processor does not support `bfsub z4.h,z16.h,z2.h'
-.*: Error: selected processor does not support `bfsub z8.h,z20.h,z1.h'
-.*: Error: selected processor does not support `bfsub z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
-.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
-.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-1.d b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-1.d
new file mode 100644
index 0000000..b1b6b7d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-1.d
@@ -0,0 +1,3 @@
+#name: Negative test with missing +sve-b16b16 flag.
+#as: -march=armv9.4-a
+#error_output: sve-b16b16-sve2-bad-1.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.l b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-1.l
index 3609fa2..3609fa2 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-1.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.s b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-1.s
index ee3b760..ee3b760 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-1.s
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.d b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.d
new file mode 100644
index 0000000..3845d5f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.d
@@ -0,0 +1,3 @@
+#name: Test Bfloat16 instructions with wrong operand combinations
+#as: -march=armv8-a+sve-b16b16+sve2
+#error_output: sve-b16b16-sve2-bad-2.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l
index ae949cf..52c7e4a 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l
@@ -165,8 +165,8 @@
 .*: Error: operand mismatch -- `bfadd z31.b,z31.s,z31.d'
 .*: Info:    did you mean this\?
 .*: Info:    	bfadd z31.h, z31.h, z31.h
-.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h},z0.h,z0.h'
-.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h ?- ?z0.h},z0.h'
+.*: Error: expected a register at operand 1 -- `bfadd { ?z0.h ?},z0.h,z0.h'
+.*: Error: expected a register at operand 1 -- `bfadd { ?z0.h-z0.h ?},z0.h'
 .*: Error: comma expected between operands at operand 3 -- `bfadd z0.h,z0.h'
 .*: Error: operand mismatch -- `bfclamp z0.b,z0.h,z0.h'
 .*: Info:    did you mean this\?
@@ -183,8 +183,8 @@
 .*: Error: operand mismatch -- `bfclamp z31.b,z31.s,z31.d'
 .*: Info:    did you mean this\?
 .*: Info:    	bfclamp z31.h, z31.h, z31.h
-.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h},z0.h,z0.h'
-.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h ?- ?z0.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfclamp { ?z0.h ?},z0.h,z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfclamp { ?z0.h-z0.h ?},z0.h'
 .*: Error: comma expected between operands at operand 3 -- `bfclamp z0.h,z0.h'
 .*: Error: operand mismatch -- `bfmla z0.b,z0.h,z0.h\[0\]'
 .*: Info:    did you mean this\?
@@ -201,8 +201,8 @@
 .*: Error: operand mismatch -- `bfmla z31.b,z31.s,z31.d\[8\]'
 .*: Info:    did you mean this\?
 .*: Info:    	bfmla z31.h, z31.h, z31.h\[8\]
-.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h},z0.h,z0.h\[1\]'
-.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h ?- ?z0.h},z0.h\[2\]'
+.*: Error: expected a register at operand 1 -- `bfmla { ?z0.h ?},z0.h,z0.h\[1\]'
+.*: Error: expected a register at operand 1 -- `bfmla { ?z0.h-z0.h ?},z0.h\[2\]'
 .*: Error: expected an SVE predicate register at operand 2 -- `bfmla z0.h,z0.h\[3\]'
 .*: Error: operand mismatch -- `bfmls z0.b,z0.h,z0.h\[0\]'
 .*: Info:    did you mean this\?
@@ -219,8 +219,8 @@
 .*: Error: operand mismatch -- `bfmls z31.b,z31.s,z31.d\[8\]'
 .*: Info:    did you mean this\?
 .*: Info:    	bfmls z31.h, z31.h, z31.h\[8\]
-.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h},z0.h,z0.h\[1\]'
-.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h ?- ?z0.h},z0.h\[2\]'
+.*: Error: expected a register at operand 1 -- `bfmls { ?z0.h ?},z0.h,z0.h\[1\]'
+.*: Error: expected a register at operand 1 -- `bfmls { ?z0.h-z0.h ?},z0.h\[2\]'
 .*: Error: expected an SVE predicate register at operand 2 -- `bfmls z0.h,z0.h\[3\]'
 .*: Error: operand mismatch -- `bfmul z0.b,z0.h,z0.h\[0\]'
 .*: Info:    did you mean this\?
@@ -237,8 +237,8 @@
 .*: Error: operand mismatch -- `bfmul z31.b,z31.s,z31.d\[8\]'
 .*: Info:    did you mean this\?
 .*: Info:    	bfmul z31.h, z31.h, z31.h\[8\]
-.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h},z0.h,z0.h\[1\]'
-.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h ?- ?z0.h},z0.h\[2\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmul { ?z0.h ?},z0.h,z0.h\[1\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmul { ?z0.h-z0.h ?},z0.h\[2\]'
 .*: Error: expected an SVE predicate register at operand 2 -- `bfmul z0.h,z0.h\[3\]'
 .*: Error: operand mismatch -- `bfsub z0.b,z0.h,z0.h'
 .*: Info:    did you mean this\?
@@ -255,8 +255,8 @@
 .*: Error: operand mismatch -- `bfsub z31.b,z31.s,z31.d'
 .*: Info:    did you mean this\?
 .*: Info:    	bfsub z31.h, z31.h, z31.h
-.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h},z0.h,z0.h'
-.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h ?- ?z0.h},z0.h'
+.*: Error: expected a register at operand 1 -- `bfsub { ?z0.h ?},z0.h,z0.h'
+.*: Error: expected a register at operand 1 -- `bfsub { ?z0.h-z0.h ?},z0.h'
 .*: Error: comma expected between operands at operand 3 -- `bfsub z0.h,z0.h'
 .*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z1.h,z3.h,z16.h'
 .*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmla z10.h,z16.h,z3.h\[7\]'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.s
index d690f12..d690f12 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.s
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/sve-b16b16-sve2.d
index 68a47f5..a0339c7 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.d
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2.d
@@ -1,7 +1,6 @@
-#name: Test of SVE2.1 and SME2.1 non-widening BFloat16 instructions.
-#as: -march=armv9.4-a+b16b16
+#name: Test of SVE2.1 non-widening BFloat16 instructions.
+#as: -march=armv8-a+sve-b16b16+sve2
 #objdump: -dr
-#xfail: *-*-*
 
 [^:]+:     file format .*
 
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.s b/gas/testsuite/gas/aarch64/sve-b16b16-sve2.s
index be8fee9..be8fee9 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.s
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2.s
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f697153..c438382 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -226,8 +226,6 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SPMU2,
   /* Performance Monitors Synchronous-Exception-Based Event Extension.  */
   AARCH64_FEATURE_SEBEP,
-  /* SVE2.1 and SME2.1 non-widening BFloat16 instructions.  */
-  AARCH64_FEATURE_B16B16,
   /* SME2.1 instructions.  */
   AARCH64_FEATURE_SME2p1,
   /* SVE2.1 instructions.  */
@@ -266,6 +264,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SME_F8F16,
   /* Non-widening half-precision FP16 to FP16 arithmetic for SME2.  */
   AARCH64_FEATURE_SME_F16F16,
+  /* SVE Z-targeting non-widening BFloat16 instructions.  */
+  AARCH64_FEATURE_SVE_B16B16,
 
   /* Virtual features.  These are used to gate instructions that are enabled
      by either of two (or more) sets of command line flags.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 47b52f9..e05d200 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1838,7 +1838,7 @@
 {                                                       \
   QLF3(S_S,NIL,S_S),                                    \
 }
-#define OP_SVE_SMSS				     \
+#define OP_SVE_HMHH				     \
 {						       \
   QLF4(S_H,P_M,S_H,S_H),				\
 }
@@ -2805,8 +2805,8 @@ static const aarch64_feature_set aarch64_feature_the =
   AARCH64_FEATURE (THE);
 static const aarch64_feature_set aarch64_feature_d128_the =
   AARCH64_FEATURES (2, D128, THE);
-static const aarch64_feature_set aarch64_feature_b16b16_sve2 =
-  AARCH64_FEATURES (2, B16B16, SVE2);
+static const aarch64_feature_set aarch64_feature_sve_b16b16_sve2 =
+  AARCH64_FEATURES (2, SVE_B16B16, SVE2);
 static const aarch64_feature_set aarch64_feature_sme2p1 =
   AARCH64_FEATURE (SME2p1);
 static const aarch64_feature_set aarch64_feature_sve2p1 =
@@ -2921,7 +2921,7 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16 =
 #define D128	  &aarch64_feature_d128
 #define THE	  &aarch64_feature_the
 #define D128_THE  &aarch64_feature_d128_the
-#define B16B16_SVE2  &aarch64_feature_b16b16_sve2
+#define B16B16_SVE2  &aarch64_feature_sve_b16b16_sve2
 #define SME2p1  &aarch64_feature_sme2p1
 #define SVE2p1  &aarch64_feature_sve2p1
 #define RCPC3	  &aarch64_feature_rcpc3
@@ -6631,16 +6631,16 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   D128_THE_INSN("rcwsswppal", 0x59e0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
   D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
 
-/* BFloat16 SVE Instructions.  */
-  B16B16_SVE2_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_SVE2_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_SVE2_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_SVE2_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_SVE2_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_SVE2_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_SVE2_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_SVE2_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_SVE2_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+/* SVE Z-targeting non-widening BFloat16 instructions.  */
+  B16B16_SVE2_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_SVE2_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_SVE2_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2),
   B16B16_SVE2_INSNC("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0),
   B16B16_SVE2_INSNC("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
   B16B16_SVE2_INSNC("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),