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| author | David Guillen Fandos <david@davidgf.net> | 2023-06-15 04:45:03 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2023-06-15 04:45:03 +0100 |
| commit | d29b94fc9f365de8002a9566df5bd8a45c7c8f1d (patch) | |
| tree | c002263374179183c7a946db845df4df087e3ce2 | |
| parent | df18f71b565c29f6f1ebd385cb1aed97d00e9660 (diff) | |
| download | binutils-d29b94fc9f365de8002a9566df5bd8a45c7c8f1d.zip binutils-d29b94fc9f365de8002a9566df5bd8a45c7c8f1d.tar.gz binutils-d29b94fc9f365de8002a9566df5bd8a45c7c8f1d.tar.bz2 | |
Add rotation instructions to MIPS Allegrex CPU
The Allegrex CPU supports bit rotation instructions as described in the
MIPS32 release 2 CPU (even though it is a MIPS-2 based CPU).
Signed-off-by: David Guillen Fandos <david@davidgf.net>
| -rw-r--r-- | gas/config/tc-mips.c | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/mips/mips.exp | 2 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 14 |
3 files changed, 9 insertions, 9 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 0439a3e..d6aae66 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -526,7 +526,7 @@ static int mips_32bitmode = 0; #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) /* True if CPU has a ror instruction. */ -#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) +#define CPU_HAS_ROR(CPU) (CPU_HAS_DROR (CPU) || (CPU) == CPU_ALLEGREX) /* True if CPU is in the Octeon family. */ #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 773e5b7..92cc386 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -509,7 +509,7 @@ mips_arch_create r3000 32 mips1 {} \ mips_arch_create r3900 32 mips1 { gpr_ilocks } \ { -march=r3900 -mtune=r3900 } { -mmips:3900 } \ { mipstx39-*-* mipstx39el-*-* } -mips_arch_create allegrex 32 mips2 { singlefloat oddspreg } \ +mips_arch_create allegrex 32 mips2 { ror singlefloat oddspreg } \ { -march=allegrex -mtune=allegrex } \ { -mmips:allegrex } mips_arch_create r4000 64 mips3 {} \ diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 3c48c0c..8eecae9 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1802,13 +1802,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0 }, -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, SMT, 0 }, -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT, 0 }, +{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33|AL, SMT, 0 }, +{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33|AL, SMT, 0 }, +{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33|AL, SMT, 0 }, {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, |