[ARM] Add support for ARMv8-R in assembler and readelf

=== Context ===

This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.

=== Patch description ===

Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.

Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.

2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

binutils/
	* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.

gas/
	* NEWS: Mention support for ARMv8-R architecture.
	* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
	(arm_extensions): Restrict pan, ras and rdma extension to
	ARMv8-A and make crypto, fp and simd extensions available to
	ARMv8-R.
	(cpu_arch_ver): Add entry for ARMv8-R.
	(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
	logic.
	* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
	* testsuite/gas/arm/armv8-ar+fp.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r+fp.d: New.
	* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
	* testsuite/gas/arm/armv8-ar+simd.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r+simd.d: New.
	* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-bad.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
	* testsuite/gas/arm/armv8-ar-bad.l: This.  Decrement line number by 1.
	* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
	architecture to assemble for and adjust error output file.
	* testsuite/gas/arm/armv8-r-bad.d: New.
	* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-barrier.s: This.
	* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
	* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
	* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
	* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
	* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-it-bad.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
	* testsuite/gas/arm/armv8-ar-it-bad.l: This.  Decrement line number
	by 1.
	* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
	architecture to assemble for and adjust error output file.
	* testsuite/gas/arm/armv8-r-it-bad.d: New.
	* testsuite/gas/arm/armv8-a.s: Rename into ...
	* testsuite/gas/arm/armv8-ar.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
	* testsuite/gas/arm/attr-march-armv8-r.d: New.
	* testsuite/gas/arm/crc32.s: Rename into ...
	* testsuite/gas/arm/crc32-armv8-ar.s: This.
	* testsuite/gas/arm/crc32.d: Rename into ...
	* testsuite/gas/arm/crc32-armv8-a.d: This.  Specify source to assemble.
	* testsuite/gas/arm/crc32-armv8-r.d: New.
	* testsuite/gas/arm/crc32-bad.s: Rename into ...
	* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
	* testsuite/gas/arm/crc32-bad.d: Rename into ...
	* testsuite/gas/arm/crc32-armv8-a-bad.d: This.  Specify source to
	assemble.
	* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
	* testsuite/gas/arm/mask_1.s: Rename into ...
	* testsuite/gas/arm/mask_1-armv8-ar.s: This.
	* testsuite/gas/arm/mask_1.d: Rename into ...
	* testsuite/gas/arm/mask_1-armv8-a.d: This.  Specify source to
	assemble.
	* testsuite/gas/arm/mask_1-armv8-r.d: new.

include/
	* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
	* opcode/arm.h (ARM_EXT2_V8A): New macro.
	(ARM_AEXT2_V8A): Rename into ...
	(ARM_AEXT2_V8AR): This.
	(ARM_AEXT2_V8A): New macro.
	(ARM_AEXT_V8R): New macro.
	(ARM_AEXT2_V8R): New macro.
	(ARM_ARCH_V8R): New macro.

46 files changed, 737 insertions, 134 deletions

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index b4672fa..4acd26b 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.
+
 2017-06-23  Nick Clifton  <nickc@redhat.com>
 
 	PR binutils/21659
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 857cf40..916c6cb 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -13712,7 +13712,7 @@ typedef struct
 
 static const char * arm_attr_tag_CPU_arch[] =
   {"Pre-v4", "v4", "v4T", "v5T", "v5TE", "v5TEJ", "v6", "v6KZ", "v6T2",
-   "v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8", "", "v8-M.baseline",
+   "v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8", "v8-R", "v8-M.baseline",
    "v8-M.mainline"};
 static const char * arm_attr_tag_ARM_ISA_use[] = {"No", "Yes"};
 static const char * arm_attr_tag_THUMB_ISA_use[] =
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 84dd4bf..919804c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,73 @@
 2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
+	* NEWS: Mention support for ARMv8-R architecture.
+	* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
+	(arm_extensions): Restrict pan, ras and rdma extension to
+	ARMv8-A and make crypto, fp and simd extensions available to
+	ARMv8-R.
+	(cpu_arch_ver): Add entry for ARMv8-R.
+	(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
+	logic.
+	* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
+	* testsuite/gas/arm/armv8-ar+fp.s: This.  Remove .arch directive.
+	* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
+	architecture to assemble for.
+	* testsuite/gas/arm/armv8-r+fp.d: New.
+	* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
+	* testsuite/gas/arm/armv8-ar+simd.s: This.  Remove .arch directive.
+	* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
+	architecture to assemble for.
+	* testsuite/gas/arm/armv8-r+simd.d: New.
+	* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
+	* testsuite/gas/arm/armv8-ar-bad.s: This.  Remove .arch directive.
+	* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
+	* testsuite/gas/arm/armv8-ar-bad.l: This.  Decrement line number by 1.
+	* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
+	architecture to assemble for and adjust error output file.
+	* testsuite/gas/arm/armv8-r-bad.d: New.
+	* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
+	* testsuite/gas/arm/armv8-ar-barrier.s: This.
+	* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
+	* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
+	* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
+	* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
+	* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
+	* testsuite/gas/arm/armv8-ar-it-bad.s: This.  Remove .arch directive.
+	* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
+	* testsuite/gas/arm/armv8-ar-it-bad.l: This.  Decrement line number
+	by 1.
+	* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
+	architecture to assemble for and adjust error output file.
+	* testsuite/gas/arm/armv8-r-it-bad.d: New.
+	* testsuite/gas/arm/armv8-a.s: Rename into ...
+	* testsuite/gas/arm/armv8-ar.s: This.  Remove .arch directive.
+	* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
+	architecture to assemble for.
+	* testsuite/gas/arm/armv8-r.d: New.
+	* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
+	* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
+	* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
+	* testsuite/gas/arm/attr-march-armv8-r.d: New.
+	* testsuite/gas/arm/crc32.s: Rename into ...
+	* testsuite/gas/arm/crc32-armv8-ar.s: This.
+	* testsuite/gas/arm/crc32.d: Rename into ...
+	* testsuite/gas/arm/crc32-armv8-a.d: This.  Specify source to assemble.
+	* testsuite/gas/arm/crc32-armv8-r.d: New.
+	* testsuite/gas/arm/crc32-bad.s: Rename into ...
+	* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
+	* testsuite/gas/arm/crc32-bad.d: Rename into ...
+	* testsuite/gas/arm/crc32-armv8-a-bad.d: This.  Specify source to
+	assemble.
+	* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
+	* testsuite/gas/arm/mask_1.s: Rename into ...
+	* testsuite/gas/arm/mask_1-armv8-ar.s: This.
+	* testsuite/gas/arm/mask_1.d: Rename into ...
+	* testsuite/gas/arm/mask_1-armv8-a.d: This.  Specify source to
+	assemble.
+	* testsuite/gas/arm/mask_1-armv8-r.d: new.
+
+2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
 	* config/tc-arm.c (arm_ext_v6m): Delete.
 	(arm_ext_v7m): Delete.
 	(arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
diff --git a/gas/NEWS b/gas/NEWS
index 2078d29..18de4d0 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -10,6 +10,8 @@
 
 * Add support for the Texas Instruments PRU processor.
 
+* Support for the ARMv8-R architecture has been added to the ARM port.
+
 Changes in 2.28:
 
 * Add support for the RISC-V architecture.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5eb088c..b0f2832 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -25913,6 +25913,7 @@ static const struct arm_arch_option_table arm_archs[] =
   ARM_ARCH_OPT ("armv8.1-a",	ARM_ARCH_V8_1A,	 FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv8.2-a",	ARM_ARCH_V8_2A,	 FPU_ARCH_VFP),
   ARM_ARCH_OPT ("armv8.3-a",	ARM_ARCH_V8_3A,	 FPU_ARCH_VFP),
+  ARM_ARCH_OPT ("armv8-r",	ARM_ARCH_V8R,	 FPU_ARCH_VFP),
   ARM_ARCH_OPT ("xscale",	ARM_ARCH_XSCALE, FPU_ARCH_VFP),
   ARM_ARCH_OPT ("iwmmxt",	ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
   ARM_ARCH_OPT ("iwmmxt2",	ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
@@ -25978,13 +25979,13 @@ static const struct arm_option_extension_value_table arm_extensions[] =
 				   ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
   ARM_EXT_OPT ("pan",	ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
 			ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
-			ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+			ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
   ARM_EXT_OPT ("ras",	ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
 			ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
-			ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+			ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
   ARM_EXT_OPT ("rdma",  FPU_ARCH_NEON_VFP_ARMV8_1,
 			ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
-			ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
+			ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
   ARM_EXT_OPT2 ("sec",	ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
 			ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
 			ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
@@ -26605,6 +26606,7 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
     {14, ARM_ARCH_V8_3A},
     {16, ARM_ARCH_V8M_BASE},
     {17, ARM_ARCH_V8M_MAIN},
+    {15, ARM_ARCH_V8R},
     {-1, ARM_ARCH_NONE}
 };
 
@@ -26950,9 +26952,7 @@ aeabi_set_public_attributes (void)
      by the base architecture.
 
      For new architectures we will have to check these tests.  */
-  gas_assert (arch <= TAG_CPU_ARCH_V8
-	      || (arch >= TAG_CPU_ARCH_V8M_BASE
-		  && arch <= TAG_CPU_ARCH_V8M_MAIN));
+  gas_assert (arch <= TAG_CPU_ARCH_V8M_MAIN);
   if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
       || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
     aeabi_set_attribute_int (Tag_DIV_use, 0);
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index d0da835..379c011 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -232,6 +232,7 @@ names are recognized:
 @code{armv8.1-a},
 @code{armv8.2-a},
 @code{armv8.3-a},
+@code{armv8-r},
 @code{iwmmxt}
 @code{iwmmxt2}
 and
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.d b/gas/testsuite/gas/arm/armv8-a+fp.d
index f77e742..1b6c743 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.d
+++ b/gas/testsuite/gas/arm/armv8-a+fp.d
@@ -1,4 +1,6 @@
 #name: Valid v8-a+fp
+#source: armv8-ar+fp.s
+#as: -march=armv8-a
 #objdump: -dr --prefix-addresses --show-raw-insn
 #skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
 
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.d b/gas/testsuite/gas/arm/armv8-a+simd.d
index 9d05566..8aa15fb 100644
--- a/gas/testsuite/gas/arm/armv8-a+simd.d
+++ b/gas/testsuite/gas/arm/armv8-a+simd.d
@@ -1,4 +1,6 @@
 #name: Valid v8-a+simdv3
+#source: armv8-ar+simd.s
+#as: -march=armv8-a
 #objdump: -dr --prefix-addresses --show-raw-insn
 #skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
 
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.d b/gas/testsuite/gas/arm/armv8-a-bad.d
index 94e130c..14d6b48 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.d
+++ b/gas/testsuite/gas/arm/armv8-a-bad.d
@@ -1,2 +1,4 @@
 #name: Invalid v8-a
-#error-output: armv8-a-bad.l
+#source: armv8-ar-bad.s
+#as: -march=armv8-a
+#error-output: armv8-ar-bad.l
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.l b/gas/testsuite/gas/arm/armv8-a-bad.l
deleted file mode 100644
index 838bbdc..0000000
--- a/gas/testsuite/gas/arm/armv8-a-bad.l
+++ /dev/null
@@ -1,96 +0,0 @@
-.*: Assembler messages:
-.*:7: Error: swp{b} use is obsoleted for ARMv8 and later
-.*:10: This coprocessor register access is deprecated in ARMv8
-.*:11: This coprocessor register access is deprecated in ARMv8
-.*:12: This coprocessor register access is deprecated in ARMv8
-.*:13: This coprocessor register access is deprecated in ARMv8
-.*:14: This coprocessor register access is deprecated in ARMv8
-.*:17: setend use is deprecated for ARMv8
-.*:20: setend use is deprecated for ARMv8
-.*:24: Error: immediate value out of range -- `hlt 0x10000'
-.*:25: Error: instruction cannot be conditional -- `hltne 0x1'
-.*:29: Error: immediate value out of range -- `hlt 64'
-.*:31: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
-.*:31: Error: instruction is always unconditional -- `hltne 0'
-.*:35: Error: r15 not allowed here -- `stlb pc,\[r0\]'
-.*:36: Error: r15 not allowed here -- `stlb r0,\[pc\]'
-.*:37: Error: r15 not allowed here -- `stlh pc,\[r0\]'
-.*:38: Error: r15 not allowed here -- `stlh r0,\[pc\]'
-.*:39: Error: r15 not allowed here -- `stl pc,\[r0\]'
-.*:40: Error: r15 not allowed here -- `stl r0,\[pc\]'
-.*:41: Error: r15 not allowed here -- `stlexb r1,pc,\[r0\]'
-.*:42: Error: r15 not allowed here -- `stlexb r1,r0,\[pc\]'
-.*:43: Error: r15 not allowed here -- `stlexb pc,r0,\[r1\]'
-.*:44: Error: registers may not be the same -- `stlexb r0,r0,\[r1\]'
-.*:45: Error: registers may not be the same -- `stlexb r0,r1,\[r0\]'
-.*:46: Error: r15 not allowed here -- `stlexh r1,pc,\[r0\]'
-.*:47: Error: r15 not allowed here -- `stlexh r1,r0,\[pc\]'
-.*:48: Error: r15 not allowed here -- `stlexh pc,r0,\[r1\]'
-.*:49: Error: registers may not be the same -- `stlexh r0,r0,\[r1\]'
-.*:50: Error: registers may not be the same -- `stlexh r0,r1,\[r0\]'
-.*:51: Error: r15 not allowed here -- `stlex r1,pc,\[r0\]'
-.*:52: Error: r15 not allowed here -- `stlex r1,r0,\[pc\]'
-.*:53: Error: r15 not allowed here -- `stlex pc,r0,\[r1\]'
-.*:54: Error: registers may not be the same -- `stlex r0,r0,\[r1\]'
-.*:55: Error: registers may not be the same -- `stlex r0,r1,\[r0\]'
-.*:56: Error: r14 not allowed here -- `stlexd r1,lr,\[r0\]'
-.*:57: Error: r15 not allowed here -- `stlexd r1,r0,\[pc\]'
-.*:58: Error: r15 not allowed here -- `stlexd pc,r0,\[r1\]'
-.*:59: Error: registers may not be the same -- `stlexd r0,r0,\[r1\]'
-.*:60: Error: registers may not be the same -- `stlexd r0,r2,\[r0\]'
-.*:61: Error: even register required -- `stlexd r0,r1,\[r2\]'
-.*:65: Error: r15 not allowed here -- `stlb pc,\[r0\]'
-.*:66: Error: r15 not allowed here -- `stlb r0,\[pc\]'
-.*:67: Error: r15 not allowed here -- `stlh pc,\[r0\]'
-.*:68: Error: r15 not allowed here -- `stlh r0,\[pc\]'
-.*:69: Error: r15 not allowed here -- `stl pc,\[r0\]'
-.*:70: Error: r15 not allowed here -- `stl r0,\[pc\]'
-.*:71: Error: r15 not allowed here -- `stlexb r1,pc,\[r0\]'
-.*:72: Error: r15 not allowed here -- `stlexb r1,r0,\[pc\]'
-.*:73: Error: r15 not allowed here -- `stlexb pc,r0,\[r1\]'
-.*:74: Error: registers may not be the same -- `stlexb r0,r0,\[r1\]'
-.*:75: Error: registers may not be the same -- `stlexb r0,r1,\[r0\]'
-.*:76: Error: r15 not allowed here -- `stlexh r1,pc,\[r0\]'
-.*:77: Error: r15 not allowed here -- `stlexh r1,r0,\[pc\]'
-.*:78: Error: r15 not allowed here -- `stlexh pc,r0,\[r1\]'
-.*:79: Error: registers may not be the same -- `stlexh r0,r0,\[r1\]'
-.*:80: Error: registers may not be the same -- `stlexh r0,r1,\[r0\]'
-.*:81: Error: r15 not allowed here -- `stlex r1,pc,\[r0\]'
-.*:82: Error: r15 not allowed here -- `stlex r1,r0,\[pc\]'
-.*:83: Error: r15 not allowed here -- `stlex pc,r0,\[r1\]'
-.*:84: Error: registers may not be the same -- `stlex r0,r0,\[r1\]'
-.*:85: Error: registers may not be the same -- `stlex r0,r1,\[r0\]'
-.*:87: Error: r15 not allowed here -- `stlexd r1,r0,\[pc\]'
-.*:88: Error: r15 not allowed here -- `stlexd pc,r0,\[r1\]'
-.*:89: Error: registers may not be the same -- `stlexd r0,r0,\[r1\]'
-.*:90: Error: registers may not be the same -- `stlexd r0,r2,\[r0\]'
-.*:95: Error: r15 not allowed here -- `ldab pc,\[r0\]'
-.*:96: Error: r15 not allowed here -- `ldab r0,\[pc\]'
-.*:97: Error: r15 not allowed here -- `ldah pc,\[r0\]'
-.*:98: Error: r15 not allowed here -- `ldah r0,\[pc\]'
-.*:99: Error: r15 not allowed here -- `lda pc,\[r0\]'
-.*:100: Error: r15 not allowed here -- `lda r0,\[pc\]'
-.*:101: Error: r15 not allowed here -- `ldaexb pc,\[r0\]'
-.*:102: Error: r15 not allowed here -- `ldaexb r0,\[pc\]'
-.*:103: Error: r15 not allowed here -- `ldaexh pc,\[r0\]'
-.*:104: Error: r15 not allowed here -- `ldaexh r0,\[pc\]'
-.*:105: Error: r15 not allowed here -- `ldaex pc,\[r0\]'
-.*:106: Error: r15 not allowed here -- `ldaex r0,\[pc\]'
-.*:107: Error: r14 not allowed here -- `ldaexd lr,\[r0\]'
-.*:108: Error: r15 not allowed here -- `ldaexd r0,\[pc\]'
-.*:109: Error: even register required -- `ldaexd r1,\[r2\]'
-.*:113: Error: r15 not allowed here -- `ldab pc,\[r0\]'
-.*:114: Error: r15 not allowed here -- `ldab r0,\[pc\]'
-.*:115: Error: r15 not allowed here -- `ldah pc,\[r0\]'
-.*:116: Error: r15 not allowed here -- `ldah r0,\[pc\]'
-.*:117: Error: r15 not allowed here -- `lda pc,\[r0\]'
-.*:118: Error: r15 not allowed here -- `lda r0,\[pc\]'
-.*:119: Error: r15 not allowed here -- `ldaexb pc,\[r0\]'
-.*:120: Error: r15 not allowed here -- `ldaexb r0,\[pc\]'
-.*:121: Error: r15 not allowed here -- `ldaexh pc,\[r0\]'
-.*:122: Error: r15 not allowed here -- `ldaexh r0,\[pc\]'
-.*:123: Error: r15 not allowed here -- `ldaex pc,\[r0\]'
-.*:124: Error: r15 not allowed here -- `ldaex r0,\[pc\]'
-.*:125: Error: r15 not allowed here -- `ldaexd r0,pc,\[r0\]'
-.*:126: Error: r15 not allowed here -- `ldaexd pc,r0,\[r0\]'
-.*:127: Error: r15 not allowed here -- `ldaexd r1,r0,\[pc\]'
diff --git a/gas/testsuite/gas/arm/armv8-a-barrier-arm.d b/gas/testsuite/gas/arm/armv8-a-barrier-arm.d
index 1a245fa..8ac6821 100644
--- a/gas/testsuite/gas/arm/armv8-a-barrier-arm.d
+++ b/gas/testsuite/gas/arm/armv8-a-barrier-arm.d
@@ -1,6 +1,6 @@
 #name: Valid v8-A barrier (ARM)
 #as: -march=armv8-a
-#source: armv8-a-barrier.s
+#source: armv8-ar-barrier.s
 #objdump: -dr --prefix-addresses --show-raw-insn
 
 .*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d b/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d
index 17c2e93..318635a 100644
--- a/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d
+++ b/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d
@@ -1,6 +1,6 @@
 #name: Valid v8-A barrier (Thumb)
 #as: -march=armv8-a -mthumb
-#source: armv8-a-barrier.s
+#source: armv8-ar-barrier.s
 #objdump: -dr --prefix-addresses --show-raw-insn
 #skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
 
diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.d b/gas/testsuite/gas/arm/armv8-a-it-bad.d
index 4789484..208ae1b 100644
--- a/gas/testsuite/gas/arm/armv8-a-it-bad.d
+++ b/gas/testsuite/gas/arm/armv8-a-it-bad.d
@@ -1,3 +1,4 @@
 #name: Deprecated IT blocks (ARM v8)
-#error-output: armv8-a-it-bad.l
-#as: -mimplicit-it=always
+#source: armv8-ar-it-bad.s
+#error-output: armv8-ar-it-bad.l
+#as: -march=armv8-a -mimplicit-it=always
diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.l b/gas/testsuite/gas/arm/armv8-a-it-bad.l
deleted file mode 100644
index d04d5ee..0000000
--- a/gas/testsuite/gas/arm/armv8-a-it-bad.l
+++ /dev/null
@@ -1,18 +0,0 @@
-.*: Assembler messages:
-.*:7: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8
-.*:15: IT blocks containing more than one conditional instruction are deprecated in ARMv8
-.*:20: IT blocks containing more than one conditional instruction are deprecated in ARMv8
-.*:30: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8
-.*:36: IT blocks containing more than one conditional instruction are deprecated in ARMv8
-.*:40: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
-.*:43: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
-.*:49: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Literal loads
-.*:52: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX using pc
-.*:55: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
-.*:55: Error: r15 not allowed here -- `addeq r0,pc,pc'
-.*:58: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
-.*:58: Error: r15 not allowed here -- `addeq pc,r0,r0'
-.*:61: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
-.*:65: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
-.*:68: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
-.*:72: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
diff --git a/gas/testsuite/gas/arm/armv8-a.d b/gas/testsuite/gas/arm/armv8-a.d
index 2119bcb..e00e31f 100644
--- a/gas/testsuite/gas/arm/armv8-a.d
+++ b/gas/testsuite/gas/arm/armv8-a.d
@@ -1,4 +1,6 @@
 #name: Valid v8-a
+#source: armv8-ar.s
+#as: -march=armv8-a
 #objdump: -dr --prefix-addresses --show-raw-insn
 
 .*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/armv8-a+fp.s b/gas/testsuite/gas/arm/armv8-ar+fp.s
index f7a5473..a3b21c7 100644
--- a/gas/testsuite/gas/arm/armv8-a+fp.s
+++ b/gas/testsuite/gas/arm/armv8-ar+fp.s
@@ -1,6 +1,5 @@
 	.syntax unified
 	.text
-	.arch armv8-a
 	.arch_extension fp
 
 	.arm
diff --git a/gas/testsuite/gas/arm/armv8-a+simd.s b/gas/testsuite/gas/arm/armv8-ar+simd.s
index 4d7bce7..8d92ce7 100644
--- a/gas/testsuite/gas/arm/armv8-a+simd.s
+++ b/gas/testsuite/gas/arm/armv8-ar+simd.s
@@ -1,5 +1,4 @@
 	.syntax unified
-	.arch armv8-a
 	.arch_extension simd
 
 	.arm
diff --git a/gas/testsuite/gas/arm/armv8-ar-bad.l b/gas/testsuite/gas/arm/armv8-ar-bad.l
new file mode 100644
index 0000000..ae9a3d1
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-ar-bad.l
@@ -0,0 +1,96 @@
+.*: Assembler messages:
+.*:6: Error: swp{b} use is obsoleted for ARMv8 and later
+.*:9: This coprocessor register access is deprecated in ARMv8
+.*:10: This coprocessor register access is deprecated in ARMv8
+.*:11: This coprocessor register access is deprecated in ARMv8
+.*:12: This coprocessor register access is deprecated in ARMv8
+.*:13: This coprocessor register access is deprecated in ARMv8
+.*:16: setend use is deprecated for ARMv8
+.*:19: setend use is deprecated for ARMv8
+.*:23: Error: immediate value out of range -- `hlt 0x10000'
+.*:24: Error: instruction cannot be conditional -- `hltne 0x1'
+.*:28: Error: immediate value out of range -- `hlt 64'
+.*:30: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
+.*:30: Error: instruction is always unconditional -- `hltne 0'
+.*:34: Error: r15 not allowed here -- `stlb pc,\[r0\]'
+.*:35: Error: r15 not allowed here -- `stlb r0,\[pc\]'
+.*:36: Error: r15 not allowed here -- `stlh pc,\[r0\]'
+.*:37: Error: r15 not allowed here -- `stlh r0,\[pc\]'
+.*:38: Error: r15 not allowed here -- `stl pc,\[r0\]'
+.*:39: Error: r15 not allowed here -- `stl r0,\[pc\]'
+.*:40: Error: r15 not allowed here -- `stlexb r1,pc,\[r0\]'
+.*:41: Error: r15 not allowed here -- `stlexb r1,r0,\[pc\]'
+.*:42: Error: r15 not allowed here -- `stlexb pc,r0,\[r1\]'
+.*:43: Error: registers may not be the same -- `stlexb r0,r0,\[r1\]'
+.*:44: Error: registers may not be the same -- `stlexb r0,r1,\[r0\]'
+.*:45: Error: r15 not allowed here -- `stlexh r1,pc,\[r0\]'
+.*:46: Error: r15 not allowed here -- `stlexh r1,r0,\[pc\]'
+.*:47: Error: r15 not allowed here -- `stlexh pc,r0,\[r1\]'
+.*:48: Error: registers may not be the same -- `stlexh r0,r0,\[r1\]'
+.*:49: Error: registers may not be the same -- `stlexh r0,r1,\[r0\]'
+.*:50: Error: r15 not allowed here -- `stlex r1,pc,\[r0\]'
+.*:51: Error: r15 not allowed here -- `stlex r1,r0,\[pc\]'
+.*:52: Error: r15 not allowed here -- `stlex pc,r0,\[r1\]'
+.*:53: Error: registers may not be the same -- `stlex r0,r0,\[r1\]'
+.*:54: Error: registers may not be the same -- `stlex r0,r1,\[r0\]'
+.*:55: Error: r14 not allowed here -- `stlexd r1,lr,\[r0\]'
+.*:56: Error: r15 not allowed here -- `stlexd r1,r0,\[pc\]'
+.*:57: Error: r15 not allowed here -- `stlexd pc,r0,\[r1\]'
+.*:58: Error: registers may not be the same -- `stlexd r0,r0,\[r1\]'
+.*:59: Error: registers may not be the same -- `stlexd r0,r2,\[r0\]'
+.*:60: Error: even register required -- `stlexd r0,r1,\[r2\]'
+.*:64: Error: r15 not allowed here -- `stlb pc,\[r0\]'
+.*:65: Error: r15 not allowed here -- `stlb r0,\[pc\]'
+.*:66: Error: r15 not allowed here -- `stlh pc,\[r0\]'
+.*:67: Error: r15 not allowed here -- `stlh r0,\[pc\]'
+.*:68: Error: r15 not allowed here -- `stl pc,\[r0\]'
+.*:69: Error: r15 not allowed here -- `stl r0,\[pc\]'
+.*:70: Error: r15 not allowed here -- `stlexb r1,pc,\[r0\]'
+.*:71: Error: r15 not allowed here -- `stlexb r1,r0,\[pc\]'
+.*:72: Error: r15 not allowed here -- `stlexb pc,r0,\[r1\]'
+.*:73: Error: registers may not be the same -- `stlexb r0,r0,\[r1\]'
+.*:74: Error: registers may not be the same -- `stlexb r0,r1,\[r0\]'
+.*:75: Error: r15 not allowed here -- `stlexh r1,pc,\[r0\]'
+.*:76: Error: r15 not allowed here -- `stlexh r1,r0,\[pc\]'
+.*:77: Error: r15 not allowed here -- `stlexh pc,r0,\[r1\]'
+.*:78: Error: registers may not be the same -- `stlexh r0,r0,\[r1\]'
+.*:79: Error: registers may not be the same -- `stlexh r0,r1,\[r0\]'
+.*:80: Error: r15 not allowed here -- `stlex r1,pc,\[r0\]'
+.*:81: Error: r15 not allowed here -- `stlex r1,r0,\[pc\]'
+.*:82: Error: r15 not allowed here -- `stlex pc,r0,\[r1\]'
+.*:83: Error: registers may not be the same -- `stlex r0,r0,\[r1\]'
+.*:84: Error: registers may not be the same -- `stlex r0,r1,\[r0\]'
+.*:86: Error: r15 not allowed here -- `stlexd r1,r0,\[pc\]'
+.*:87: Error: r15 not allowed here -- `stlexd pc,r0,\[r1\]'
+.*:88: Error: registers may not be the same -- `stlexd r0,r0,\[r1\]'
+.*:89: Error: registers may not be the same -- `stlexd r0,r2,\[r0\]'
+.*:94: Error: r15 not allowed here -- `ldab pc,\[r0\]'
+.*:95: Error: r15 not allowed here -- `ldab r0,\[pc\]'
+.*:96: Error: r15 not allowed here -- `ldah pc,\[r0\]'
+.*:97: Error: r15 not allowed here -- `ldah r0,\[pc\]'
+.*:98: Error: r15 not allowed here -- `lda pc,\[r0\]'
+.*:99: Error: r15 not allowed here -- `lda r0,\[pc\]'
+.*:100: Error: r15 not allowed here -- `ldaexb pc,\[r0\]'
+.*:101: Error: r15 not allowed here -- `ldaexb r0,\[pc\]'
+.*:102: Error: r15 not allowed here -- `ldaexh pc,\[r0\]'
+.*:103: Error: r15 not allowed here -- `ldaexh r0,\[pc\]'
+.*:104: Error: r15 not allowed here -- `ldaex pc,\[r0\]'
+.*:105: Error: r15 not allowed here -- `ldaex r0,\[pc\]'
+.*:106: Error: r14 not allowed here -- `ldaexd lr,\[r0\]'
+.*:107: Error: r15 not allowed here -- `ldaexd r0,\[pc\]'
+.*:108: Error: even register required -- `ldaexd r1,\[r2\]'
+.*:112: Error: r15 not allowed here -- `ldab pc,\[r0\]'
+.*:113: Error: r15 not allowed here -- `ldab r0,\[pc\]'
+.*:114: Error: r15 not allowed here -- `ldah pc,\[r0\]'
+.*:115: Error: r15 not allowed here -- `ldah r0,\[pc\]'
+.*:116: Error: r15 not allowed here -- `lda pc,\[r0\]'
+.*:117: Error: r15 not allowed here -- `lda r0,\[pc\]'
+.*:118: Error: r15 not allowed here -- `ldaexb pc,\[r0\]'
+.*:119: Error: r15 not allowed here -- `ldaexb r0,\[pc\]'
+.*:120: Error: r15 not allowed here -- `ldaexh pc,\[r0\]'
+.*:121: Error: r15 not allowed here -- `ldaexh r0,\[pc\]'
+.*:122: Error: r15 not allowed here -- `ldaex pc,\[r0\]'
+.*:123: Error: r15 not allowed here -- `ldaex r0,\[pc\]'
+.*:124: Error: r15 not allowed here -- `ldaexd r0,pc,\[r0\]'
+.*:125: Error: r15 not allowed here -- `ldaexd pc,r0,\[r0\]'
+.*:126: Error: r15 not allowed here -- `ldaexd r1,r0,\[pc\]'
diff --git a/gas/testsuite/gas/arm/armv8-a-bad.s b/gas/testsuite/gas/arm/armv8-ar-bad.s
index 90919e7..7952861 100644
--- a/gas/testsuite/gas/arm/armv8-a-bad.s
+++ b/gas/testsuite/gas/arm/armv8-ar-bad.s
@@ -1,6 +1,5 @@
 	.syntax unified
 	.text
-	.arch armv8-a
 
 	// SWP
 	.arm
diff --git a/gas/testsuite/gas/arm/armv8-a-barrier.s b/gas/testsuite/gas/arm/armv8-ar-barrier.s
index f7b71c0..f7b71c0 100644
--- a/gas/testsuite/gas/arm/armv8-a-barrier.s
+++ b/gas/testsuite/gas/arm/armv8-ar-barrier.s
diff --git a/gas/testsuite/gas/arm/armv8-ar-it-bad.l b/gas/testsuite/gas/arm/armv8-ar-it-bad.l
new file mode 100644
index 0000000..a69938d
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-ar-it-bad.l
@@ -0,0 +1,18 @@
+.*: Assembler messages:
+.*:6: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8
+.*:14: IT blocks containing more than one conditional instruction are deprecated in ARMv8
+.*:19: IT blocks containing more than one conditional instruction are deprecated in ARMv8
+.*:29: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8
+.*:35: IT blocks containing more than one conditional instruction are deprecated in ARMv8
+.*:39: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
+.*:42: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions
+.*:48: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Literal loads
+.*:51: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX using pc
+.*:54: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
+.*:54: Error: r15 not allowed here -- `addeq r0,pc,pc'
+.*:57: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM
+.*:57: Error: r15 not allowed here -- `addeq pc,r0,r0'
+.*:60: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
+.*:64: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
+.*:67: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
+.*:71: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: ADD/SUB sp, sp #imm
diff --git a/gas/testsuite/gas/arm/armv8-a-it-bad.s b/gas/testsuite/gas/arm/armv8-ar-it-bad.s
index d1bc07a..9864bf8 100644
--- a/gas/testsuite/gas/arm/armv8-a-it-bad.s
+++ b/gas/testsuite/gas/arm/armv8-ar-it-bad.s
@@ -1,5 +1,4 @@
 .syntax unified
-.arch armv8-a
 
 .thumb
 @ Wide instruction in IT block is deprecated.
diff --git a/gas/testsuite/gas/arm/armv8-a.s b/gas/testsuite/gas/arm/armv8-ar.s
index 3217a8a..3217a8a 100644
--- a/gas/testsuite/gas/arm/armv8-a.s
+++ b/gas/testsuite/gas/arm/armv8-ar.s
diff --git a/gas/testsuite/gas/arm/armv8-r+fp.d b/gas/testsuite/gas/arm/armv8-r+fp.d
new file mode 100644
index 0000000..34cfd34
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-r+fp.d
@@ -0,0 +1,117 @@
+#name: Valid v8-r+fp
+#source: armv8-ar+fp.s
+#as: -march=armv8-r
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> fe000a00 	vseleq.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe500aa0 	vselvs.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2ffa0f 	vselge.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7ffaaf 	vselgt.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe000b00 	vseleq.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe500ba0 	vselvs.f64	d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe2ffb0f 	vselge.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe7ffbaf 	vselgt.f64	d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe800a00 	vmaxnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec00aa0 	vmaxnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8ffa0f 	vmaxnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecffaaf 	vmaxnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe800b00 	vmaxnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec00ba0 	vmaxnm.f64	d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8ffb0f 	vmaxnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecffbaf 	vmaxnm.f64	d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe800a40 	vminnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec00ae0 	vminnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8ffa4f 	vminnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecffaef 	vminnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe800b40 	vminnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec00be0 	vminnm.f64	d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8ffb4f 	vminnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecffbef 	vminnm.f64	d31, d31, d31
+0[0-9a-f]+ <[^>]+> febc0ac0 	vcvta.s32.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fefd0ae0 	vcvtn.s32.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febefa4f 	vcvtp.u32.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefffa6f 	vcvtm.u32.f32	s31, s31
+0[0-9a-f]+ <[^>]+> febc0bc0 	vcvta.s32.f64	s0, d0
+0[0-9a-f]+ <[^>]+> fefd0be0 	vcvtn.s32.f64	s1, d16
+0[0-9a-f]+ <[^>]+> febefb4f 	vcvtp.u32.f64	s30, d15
+0[0-9a-f]+ <[^>]+> fefffb6f 	vcvtm.u32.f64	s31, d31
+0[0-9a-f]+ <[^>]+> eeb60ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef70a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> 0eb6fa4f 	vrintreq.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb80a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef90a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febafa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefbfa6f 	vrintm.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb60bc0 	vrintz.f64	d0, d0
+0[0-9a-f]+ <[^>]+> eeb71b41 	vrintx.f64	d1, d1
+0[0-9a-f]+ <[^>]+> 0ef6eb6e 	vrintreq.f64	d30, d30
+0[0-9a-f]+ <[^>]+> feb80b40 	vrinta.f64	d0, d0
+0[0-9a-f]+ <[^>]+> feb91b41 	vrintn.f64	d1, d1
+0[0-9a-f]+ <[^>]+> fefaeb6e 	vrintp.f64	d30, d30
+0[0-9a-f]+ <[^>]+> fefbfb6f 	vrintm.f64	d31, d31
+0[0-9a-f]+ <[^>]+> eeb30bc0 	vcvtt.f16.f64	s0, d0
+0[0-9a-f]+ <[^>]+> eef30b60 	vcvtb.f16.f64	s1, d16
+0[0-9a-f]+ <[^>]+> eeb3fbcf 	vcvtt.f16.f64	s30, d15
+0[0-9a-f]+ <[^>]+> eef3fb6f 	vcvtb.f16.f64	s31, d31
+0[0-9a-f]+ <[^>]+> eeb20bc0 	vcvtt.f64.f16	d0, s0
+0[0-9a-f]+ <[^>]+> eef20b60 	vcvtb.f64.f16	d16, s1
+0[0-9a-f]+ <[^>]+> eeb2fbcf 	vcvtt.f64.f16	d15, s30
+0[0-9a-f]+ <[^>]+> eef2fb6f 	vcvtb.f64.f16	d31, s31
+0[0-9a-f]+ <[^>]+> fe00 0a00 	vseleq.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fe50 0aa0 	vselvs.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe2f fa0f 	vselge.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fe7f faaf 	vselgt.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe00 0b00 	vseleq.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fe50 0ba0 	vselvs.f64	d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe2f fb0f 	vselge.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fe7f fbaf 	vselgt.f64	d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe80 0a00 	vmaxnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 	vmaxnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f 	vmaxnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf 	vmaxnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b00 	vmaxnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec0 0ba0 	vmaxnm.f64	d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8f fb0f 	vmaxnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecf fbaf 	vmaxnm.f64	d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe80 0a40 	vminnm.f32	s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 	vminnm.f32	s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f 	vminnm.f32	s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef 	vminnm.f32	s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b40 	vminnm.f64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec0 0be0 	vminnm.f64	d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8f fb4f 	vminnm.f64	d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecf fbef 	vminnm.f64	d31, d31, d31
+0[0-9a-f]+ <[^>]+> febc 0ac0 	vcvta.s32.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fefd 0ae0 	vcvtn.s32.f32	s1, s1
+0[0-9a-f]+ <[^>]+> febe fa4f 	vcvtp.u32.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feff fa6f 	vcvtm.u32.f32	s31, s31
+0[0-9a-f]+ <[^>]+> febc 0bc0 	vcvta.s32.f64	s0, d0
+0[0-9a-f]+ <[^>]+> fefd 0be0 	vcvtn.s32.f64	s1, d16
+0[0-9a-f]+ <[^>]+> febe fb4f 	vcvtp.u32.f64	s30, d15
+0[0-9a-f]+ <[^>]+> feff fb6f 	vcvtm.u32.f64	s31, d31
+0[0-9a-f]+ <[^>]+> eeb6 0ac0 	vrintz.f32	s0, s0
+0[0-9a-f]+ <[^>]+> eef7 0a60 	vrintx.f32	s1, s1
+0[0-9a-f]+ <[^>]+> eeb6 fa4f 	vrintr.f32	s30, s30
+0[0-9a-f]+ <[^>]+> feb8 0a40 	vrinta.f32	s0, s0
+0[0-9a-f]+ <[^>]+> fef9 0a60 	vrintn.f32	s1, s1
+0[0-9a-f]+ <[^>]+> feba fa4f 	vrintp.f32	s30, s30
+0[0-9a-f]+ <[^>]+> fefb fa6f 	vrintm.f32	s31, s31
+0[0-9a-f]+ <[^>]+> eeb6 0bc0 	vrintz.f64	d0, d0
+0[0-9a-f]+ <[^>]+> eeb7 1b41 	vrintx.f64	d1, d1
+0[0-9a-f]+ <[^>]+> eef6 eb6e 	vrintr.f64	d30, d30
+0[0-9a-f]+ <[^>]+> feb8 0b40 	vrinta.f64	d0, d0
+0[0-9a-f]+ <[^>]+> feb9 1b41 	vrintn.f64	d1, d1
+0[0-9a-f]+ <[^>]+> fefa eb6e 	vrintp.f64	d30, d30
+0[0-9a-f]+ <[^>]+> fefb fb6f 	vrintm.f64	d31, d31
+0[0-9a-f]+ <[^>]+> eeb3 0bc0 	vcvtt.f16.f64	s0, d0
+0[0-9a-f]+ <[^>]+> eef3 0b60 	vcvtb.f16.f64	s1, d16
+0[0-9a-f]+ <[^>]+> eeb3 fbcf 	vcvtt.f16.f64	s30, d15
+0[0-9a-f]+ <[^>]+> eef3 fb6f 	vcvtb.f16.f64	s31, d31
+0[0-9a-f]+ <[^>]+> eeb2 0bc0 	vcvtt.f64.f16	d0, s0
+0[0-9a-f]+ <[^>]+> eef2 0b60 	vcvtb.f64.f16	d16, s1
+0[0-9a-f]+ <[^>]+> eeb2 fbcf 	vcvtt.f64.f16	d15, s30
+0[0-9a-f]+ <[^>]+> eef2 fb6f 	vcvtb.f64.f16	d31, s31
diff --git a/gas/testsuite/gas/arm/armv8-r+simd.d b/gas/testsuite/gas/arm/armv8-r+simd.d
new file mode 100644
index 0000000..4237218
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-r+simd.d
@@ -0,0 +1,81 @@
+#name: Valid v8-r+simdv3
+#source: armv8-ar+simd.s
+#as: -march=armv8-r
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f3000f10 	vmaxnm.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3400fb0 	vmaxnm.f32	d16, d16, d16
+0[0-9a-f]+ <[^>]+> f30fff1f 	vmaxnm.f32	d15, d15, d15
+0[0-9a-f]+ <[^>]+> f34fffbf 	vmaxnm.f32	d31, d31, d31
+0[0-9a-f]+ <[^>]+> f3000f50 	vmaxnm.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3400ff0 	vmaxnm.f32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f30eef5e 	vmaxnm.f32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f34eeffe 	vmaxnm.f32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3200f10 	vminnm.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3600fb0 	vminnm.f32	d16, d16, d16
+0[0-9a-f]+ <[^>]+> f32fff1f 	vminnm.f32	d15, d15, d15
+0[0-9a-f]+ <[^>]+> f36fffbf 	vminnm.f32	d31, d31, d31
+0[0-9a-f]+ <[^>]+> f3200f50 	vminnm.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3600ff0 	vminnm.f32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> f32eef5e 	vminnm.f32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> f36eeffe 	vminnm.f32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3bb0000 	vcvta.s32.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f3fb0120 	vcvtn.s32.f32	d16, d16
+0[0-9a-f]+ <[^>]+> f3bbf28f 	vcvtp.u32.f32	d15, d15
+0[0-9a-f]+ <[^>]+> f3fbf3af 	vcvtm.u32.f32	d31, d31
+0[0-9a-f]+ <[^>]+> f3bb0040 	vcvta.s32.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3fb0160 	vcvtn.s32.f32	q8, q8
+0[0-9a-f]+ <[^>]+> f3bbe2ce 	vcvtp.u32.f32	q7, q7
+0[0-9a-f]+ <[^>]+> f3fbe3ee 	vcvtm.u32.f32	q15, q15
+0[0-9a-f]+ <[^>]+> f3ba0500 	vrinta.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f3fa0420 	vrintn.f32	d16, d16
+0[0-9a-f]+ <[^>]+> f3baf68f 	vrintm.f32	d15, d15
+0[0-9a-f]+ <[^>]+> f3faf7af 	vrintp.f32	d31, d31
+0[0-9a-f]+ <[^>]+> f3ba04af 	vrintx.f32	d0, d31
+0[0-9a-f]+ <[^>]+> f3fa058f 	vrintz.f32	d16, d15
+0[0-9a-f]+ <[^>]+> f3ba0540 	vrinta.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3fa0460 	vrintn.f32	q8, q8
+0[0-9a-f]+ <[^>]+> f3bae6ce 	vrintm.f32	q7, q7
+0[0-9a-f]+ <[^>]+> f3fae7ee 	vrintp.f32	q15, q15
+0[0-9a-f]+ <[^>]+> f3ba04ee 	vrintx.f32	q0, q15
+0[0-9a-f]+ <[^>]+> f3fa05ce 	vrintz.f32	q8, q7
+0[0-9a-f]+ <[^>]+> ff00 0f10 	vmaxnm.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> ff40 0fb0 	vmaxnm.f32	d16, d16, d16
+0[0-9a-f]+ <[^>]+> ff0f ff1f 	vmaxnm.f32	d15, d15, d15
+0[0-9a-f]+ <[^>]+> ff4f ffbf 	vmaxnm.f32	d31, d31, d31
+0[0-9a-f]+ <[^>]+> ff00 0f50 	vmaxnm.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff40 0ff0 	vmaxnm.f32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff0e ef5e 	vmaxnm.f32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff4e effe 	vmaxnm.f32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff20 0f10 	vminnm.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> ff60 0fb0 	vminnm.f32	d16, d16, d16
+0[0-9a-f]+ <[^>]+> ff2f ff1f 	vminnm.f32	d15, d15, d15
+0[0-9a-f]+ <[^>]+> ff6f ffbf 	vminnm.f32	d31, d31, d31
+0[0-9a-f]+ <[^>]+> ff20 0f50 	vminnm.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff60 0ff0 	vminnm.f32	q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff2e ef5e 	vminnm.f32	q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff6e effe 	vminnm.f32	q15, q15, q15
+0[0-9a-f]+ <[^>]+> ffbb 0000 	vcvta.s32.f32	d0, d0
+0[0-9a-f]+ <[^>]+> fffb 0120 	vcvtn.s32.f32	d16, d16
+0[0-9a-f]+ <[^>]+> ffbb f28f 	vcvtp.u32.f32	d15, d15
+0[0-9a-f]+ <[^>]+> fffb f3af 	vcvtm.u32.f32	d31, d31
+0[0-9a-f]+ <[^>]+> ffbb 0040 	vcvta.s32.f32	q0, q0
+0[0-9a-f]+ <[^>]+> fffb 0160 	vcvtn.s32.f32	q8, q8
+0[0-9a-f]+ <[^>]+> ffbb e2ce 	vcvtp.u32.f32	q7, q7
+0[0-9a-f]+ <[^>]+> fffb e3ee 	vcvtm.u32.f32	q15, q15
+0[0-9a-f]+ <[^>]+> ffba 0500 	vrinta.f32	d0, d0
+0[0-9a-f]+ <[^>]+> fffa 0420 	vrintn.f32	d16, d16
+0[0-9a-f]+ <[^>]+> ffba f68f 	vrintm.f32	d15, d15
+0[0-9a-f]+ <[^>]+> fffa f7af 	vrintp.f32	d31, d31
+0[0-9a-f]+ <[^>]+> ffba 04af 	vrintx.f32	d0, d31
+0[0-9a-f]+ <[^>]+> fffa 058f 	vrintz.f32	d16, d15
+0[0-9a-f]+ <[^>]+> ffba 0540 	vrinta.f32	q0, q0
+0[0-9a-f]+ <[^>]+> fffa 0460 	vrintn.f32	q8, q8
+0[0-9a-f]+ <[^>]+> ffba e6ce 	vrintm.f32	q7, q7
+0[0-9a-f]+ <[^>]+> fffa e7ee 	vrintp.f32	q15, q15
+0[0-9a-f]+ <[^>]+> ffba 04ee 	vrintx.f32	q0, q15
+0[0-9a-f]+ <[^>]+> fffa 05ce 	vrintz.f32	q8, q7
diff --git a/gas/testsuite/gas/arm/armv8-r-bad.d b/gas/testsuite/gas/arm/armv8-r-bad.d
new file mode 100644
index 0000000..332c791
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-r-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid v8-r
+#source: armv8-ar-bad.s
+#as: -march=armv8-r
+#error-output: armv8-ar-bad.l
diff --git a/gas/testsuite/gas/arm/armv8-r-barrier-arm.d b/gas/testsuite/gas/arm/armv8-r-barrier-arm.d
new file mode 100644
index 0000000..0d361eb
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-r-barrier-arm.d
@@ -0,0 +1,24 @@
+#name: Valid v8-R barrier (ARM)
+#as: -march=armv8-r
+#source: armv8-ar-barrier.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f57ff04d 	dsb	ld
+0[0-9a-f]+ <[^>]+> f57ff049 	dsb	ishld
+0[0-9a-f]+ <[^>]+> f57ff045 	dsb	nshld
+0[0-9a-f]+ <[^>]+> f57ff041 	dsb	oshld
+0[0-9a-f]+ <[^>]+> f57ff05d 	dmb	ld
+0[0-9a-f]+ <[^>]+> f57ff059 	dmb	ishld
+0[0-9a-f]+ <[^>]+> f57ff055 	dmb	nshld
+0[0-9a-f]+ <[^>]+> f57ff051 	dmb	oshld
+0[0-9a-f]+ <[^>]+> f57ff04d 	dsb	ld
+0[0-9a-f]+ <[^>]+> f57ff049 	dsb	ishld
+0[0-9a-f]+ <[^>]+> f57ff045 	dsb	nshld
+0[0-9a-f]+ <[^>]+> f57ff041 	dsb	oshld
+0[0-9a-f]+ <[^>]+> f57ff05d 	dmb	ld
+0[0-9a-f]+ <[^>]+> f57ff059 	dmb	ishld
+0[0-9a-f]+ <[^>]+> f57ff055 	dmb	nshld
+0[0-9a-f]+ <[^>]+> f57ff051 	dmb	oshld
diff --git a/gas/testsuite/gas/arm/armv8-r-barrier-thumb.d b/gas/testsuite/gas/arm/armv8-r-barrier-thumb.d
new file mode 100644
index 0000000..5478ff6
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-r-barrier-thumb.d
@@ -0,0 +1,25 @@
+#name: Valid v8-R barrier (Thumb)
+#as: -march=armv8-r -mthumb
+#source: armv8-ar-barrier.s
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f3bf 8f4d 	dsb	ld
+0[0-9a-f]+ <[^>]+> f3bf 8f49 	dsb	ishld
+0[0-9a-f]+ <[^>]+> f3bf 8f45 	dsb	nshld
+0[0-9a-f]+ <[^>]+> f3bf 8f41 	dsb	oshld
+0[0-9a-f]+ <[^>]+> f3bf 8f5d 	dmb	ld
+0[0-9a-f]+ <[^>]+> f3bf 8f59 	dmb	ishld
+0[0-9a-f]+ <[^>]+> f3bf 8f55 	dmb	nshld
+0[0-9a-f]+ <[^>]+> f3bf 8f51 	dmb	oshld
+0[0-9a-f]+ <[^>]+> f3bf 8f4d 	dsb	ld
+0[0-9a-f]+ <[^>]+> f3bf 8f49 	dsb	ishld
+0[0-9a-f]+ <[^>]+> f3bf 8f45 	dsb	nshld
+0[0-9a-f]+ <[^>]+> f3bf 8f41 	dsb	oshld
+0[0-9a-f]+ <[^>]+> f3bf 8f5d 	dmb	ld
+0[0-9a-f]+ <[^>]+> f3bf 8f59 	dmb	ishld
+0[0-9a-f]+ <[^>]+> f3bf 8f55 	dmb	nshld
+0[0-9a-f]+ <[^>]+> f3bf 8f51 	dmb	oshld
diff --git a/gas/testsuite/gas/arm/armv8-r-it-bad.d b/gas/testsuite/gas/arm/armv8-r-it-bad.d
new file mode 100644
index 0000000..ae24051
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-r-it-bad.d
@@ -0,0 +1,4 @@
+#name: Deprecated IT blocks (ARM v8)
+#source: armv8-ar-it-bad.s
+#error-output: armv8-ar-it-bad.l
+#as: -march=armv8-r -mimplicit-it=always
diff --git a/gas/testsuite/gas/arm/armv8-r.d b/gas/testsuite/gas/arm/armv8-r.d
new file mode 100644
index 0000000..7a7a426
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8-r.d
@@ -0,0 +1,104 @@
+#name: Valid v8-r
+#source: armv8-ar.s
+#as: -march=armv8-r
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> e320f005 	sevl
+0[0-9a-f]+ <[^>]+> e1000070 	hlt	0x0000
+0[0-9a-f]+ <[^>]+> e100007f 	hlt	0x000f
+0[0-9a-f]+ <[^>]+> e10fff70 	hlt	0xfff0
+0[0-9a-f]+ <[^>]+> e1c0fc90 	stlb	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1c1fc91 	stlb	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1cefc9e 	stlb	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1e0fc90 	stlh	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1e1fc91 	stlh	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1eefc9e 	stlh	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e180fc90 	stl	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e181fc91 	stl	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e18efc9e 	stl	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1ce0e91 	stlexb	r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e1c01e9e 	stlexb	r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e1c1ee90 	stlexb	lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e1ee0e91 	stlexh	r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e1e01e9e 	stlexh	r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e1e1ee90 	stlexh	lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e18e0e91 	stlex	r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e1801e9e 	stlex	r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e181ee90 	stlex	lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e1ae0e92 	stlexd	r0, r2, r3, \[lr\]
+0[0-9a-f]+ <[^>]+> e1a01e9c 	stlexd	r1, ip, sp, \[r0\]
+0[0-9a-f]+ <[^>]+> e1a1ee90 	stlexd	lr, r0, r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1d00c9f 	ldab	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1d11c9f 	ldab	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1deec9f 	ldab	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1f00c9f 	ldah	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1f11c9f 	ldah	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1feec9f 	ldah	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1900c9f 	lda	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1911c9f 	lda	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e19eec9f 	lda	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1d00e9f 	ldaexb	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1d11e9f 	ldaexb	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1deee9f 	ldaexb	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1f00e9f 	ldaexh	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1f11e9f 	ldaexh	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e1feee9f 	ldaexh	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1900e9f 	ldaex	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e1911e9f 	ldaex	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e19eee9f 	ldaex	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e1b00e9f 	ldaexd	r0, r1, \[r0\]
+0[0-9a-f]+ <[^>]+> e1b12e9f 	ldaexd	r2, r3, \[r1\]
+0[0-9a-f]+ <[^>]+> e1bece9f 	ldaexd	ip, sp, \[lr\]
+0[0-9a-f]+ <[^>]+> bf50      	sevl
+0[0-9a-f]+ <[^>]+> bf50      	sevl
+0[0-9a-f]+ <[^>]+> f3af 8005 	sevl.w
+0[0-9a-f]+ <[^>]+> f78f 8001 	dcps1
+0[0-9a-f]+ <[^>]+> f78f 8002 	dcps2
+0[0-9a-f]+ <[^>]+> f78f 8003 	dcps3
+0[0-9a-f]+ <[^>]+> ba80      	hlt	0x0000
+0[0-9a-f]+ <[^>]+> babf      	hlt	0x003f
+0[0-9a-f]+ <[^>]+> e8c0 0f8f 	stlb	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 1f8f 	stlb	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce ef8f 	stlb	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 0f9f 	stlh	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 1f9f 	stlh	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce ef9f 	stlh	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 0faf 	stl	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 1faf 	stl	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce efaf 	stl	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8ce 1fc0 	stlexb	r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 efc1 	stlexb	r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 0fce 	stlexb	lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce 1fd0 	stlexh	r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 efd1 	stlexh	r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 0fde 	stlexh	lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce 1fe0 	stlex	r0, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 efe1 	stlex	r1, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 0fee 	stlex	lr, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e8ce 11f0 	stlexd	r0, r1, r1, \[lr\]
+0[0-9a-f]+ <[^>]+> e8c0 eef1 	stlexd	r1, lr, lr, \[r0\]
+0[0-9a-f]+ <[^>]+> e8c1 00fe 	stlexd	lr, r0, r0, \[r1\]
+0[0-9a-f]+ <[^>]+> e8d0 0f8f 	ldab	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1f8f 	ldab	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de ef8f 	ldab	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0f9f 	ldah	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1f9f 	ldah	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de ef9f 	ldah	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0faf 	lda	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1faf 	lda	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de efaf 	lda	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0fcf 	ldaexb	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1fcf 	ldaexb	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de efcf 	ldaexb	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0fdf 	ldaexh	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1fdf 	ldaexh	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de efdf 	ldaexh	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 0fef 	ldaex	r0, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1fef 	ldaex	r1, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de efef 	ldaex	lr, \[lr\]
+0[0-9a-f]+ <[^>]+> e8d0 01ff 	ldaexd	r0, r1, \[r0\]
+0[0-9a-f]+ <[^>]+> e8d1 1eff 	ldaexd	r1, lr, \[r1\]
+0[0-9a-f]+ <[^>]+> e8de e0ff 	ldaexd	lr, r0, \[lr\]
diff --git a/gas/testsuite/gas/arm/attr-march-armv8-r+crypto.d b/gas/testsuite/gas/arm/attr-march-armv8-r+crypto.d
new file mode 100644
index 0000000..e2d83a0
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8-r+crypto.d
@@ -0,0 +1,18 @@
+# name: attributes for -march=armv8-r+crypto
+# source: blank.s
+# as: -march=armv8-r+crypto
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "8-R"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-march-armv8-r+fp.d b/gas/testsuite/gas/arm/attr-march-armv8-r+fp.d
new file mode 100644
index 0000000..e7a8446
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8-r+fp.d
@@ -0,0 +1,17 @@
+# name: attributes for -march=armv8-r+fp
+# source: blank.s
+# as: -march=armv8-r+fp
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "8-R"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-march-armv8-r+simd.d b/gas/testsuite/gas/arm/attr-march-armv8-r+simd.d
new file mode 100644
index 0000000..e09091c
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8-r+simd.d
@@ -0,0 +1,18 @@
+# name: attributes for -march=armv8-r+simd
+# source: blank.s
+# as: -march=armv8-r+simd
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "8-R"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/attr-march-armv8-r.d b/gas/testsuite/gas/arm/attr-march-armv8-r.d
new file mode 100644
index 0000000..820f32b
--- /dev/null
+++ b/gas/testsuite/gas/arm/attr-march-armv8-r.d
@@ -0,0 +1,16 @@
+# name: attributes for -march=armv8-r
+# source: blank.s
+# as: -march=armv8-r
+# readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "8-R"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/crc32-bad.d b/gas/testsuite/gas/arm/crc32-armv8-a-bad.d
index 1a4b830..18d4844 100644
--- a/gas/testsuite/gas/arm/crc32-bad.d
+++ b/gas/testsuite/gas/arm/crc32-armv8-a-bad.d
@@ -1,5 +1,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
-#name: Unpredictable ARMv8 CRC32 instructions.
+#name: Unpredictable ARMv8-A CRC32 instructions.
+#source: crc32-armv8-ar-bad.s
 #as: -march=armv8-a+crc
 #stderr: crc32-bad.l
 #not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
diff --git a/gas/testsuite/gas/arm/crc32.d b/gas/testsuite/gas/arm/crc32-armv8-a.d
index 9e6c1c2..b09942e 100644
--- a/gas/testsuite/gas/arm/crc32.d
+++ b/gas/testsuite/gas/arm/crc32-armv8-a.d
@@ -1,5 +1,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
-#name: ARMv8 CRC32 instructions
+#name: ARMv8-A CRC32 instructions
+#source: crc32-armv8-ar.s
 #as: -march=armv8-a+crc
 #not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
 
diff --git a/gas/testsuite/gas/arm/crc32-bad.s b/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s
index 4e497e3..4e497e3 100644
--- a/gas/testsuite/gas/arm/crc32-bad.s
+++ b/gas/testsuite/gas/arm/crc32-armv8-ar-bad.s
diff --git a/gas/testsuite/gas/arm/crc32.s b/gas/testsuite/gas/arm/crc32-armv8-ar.s
index 63c1d68..63c1d68 100644
--- a/gas/testsuite/gas/arm/crc32.s
+++ b/gas/testsuite/gas/arm/crc32-armv8-ar.s
diff --git a/gas/testsuite/gas/arm/crc32-armv8-r-bad.d b/gas/testsuite/gas/arm/crc32-armv8-r-bad.d
new file mode 100644
index 0000000..a1a4f61
--- /dev/null
+++ b/gas/testsuite/gas/arm/crc32-armv8-r-bad.d
@@ -0,0 +1,23 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: Unpredictable ARMv8-R CRC32 instructions.
+#source: crc32-armv8-ar-bad.s
+#as: -march=armv8-r+crc
+#stderr: crc32-bad.l
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format .*arm.*
+
+
+Disassembly of section .text:
+0+0 <[^>]*> e101f042 	crc32b	pc, r1, r2	; <UNPREDICTABLE>
+0+4 <[^>]*> e12f0042 	crc32h	r0, pc, r2	; <UNPREDICTABLE>
+0+8 <[^>]*> e141004f 	crc32w	r0, r1, pc	; <UNPREDICTABLE>
+0+c <[^>]*> e10f0242 	crc32cb	r0, pc, r2	; <UNPREDICTABLE>
+0+10 <[^>]*> e121f242 	crc32ch	pc, r1, r2	; <UNPREDICTABLE>
+0+14 <[^>]*> e14f0242 	crc32cw	r0, pc, r2	; <UNPREDICTABLE>
+0+18 <[^>]*> fac1 fd82 	crc32b	sp, r1, r2	; <UNPREDICTABLE>
+0+1c <[^>]*> facf f092 	crc32h	r0, pc, r2	; <UNPREDICTABLE>
+0+20 <[^>]*> fac1 f0ad 	crc32w	r0, r1, sp	; <UNPREDICTABLE>
+0+24 <[^>]*> fadf f082 	crc32cb	r0, pc, r2	; <UNPREDICTABLE>
+0+28 <[^>]*> fad1 fd92 	crc32ch	sp, r1, r2	; <UNPREDICTABLE>
+0+2c <[^>]*> fadf f0a2 	crc32cw	r0, pc, r2	; <UNPREDICTABLE>
diff --git a/gas/testsuite/gas/arm/crc32-armv8-r.d b/gas/testsuite/gas/arm/crc32-armv8-r.d
new file mode 100644
index 0000000..b179821
--- /dev/null
+++ b/gas/testsuite/gas/arm/crc32-armv8-r.d
@@ -0,0 +1,23 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARMv8-R CRC32 instructions
+#source: crc32-armv8-ar.s
+#as: -march=armv8-r+crc
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: *file format .*arm.*
+
+
+Disassembly of section .text:
+0+0 <[^>]*> e1010042 	crc32b	r0, r1, r2
+0+4 <[^>]*> e1210042 	crc32h	r0, r1, r2
+0+8 <[^>]*> e1410042 	crc32w	r0, r1, r2
+0+c <[^>]*> e1010242 	crc32cb	r0, r1, r2
+0+10 <[^>]*> e1210242 	crc32ch	r0, r1, r2
+0+14 <[^>]*> e1410242 	crc32cw	r0, r1, r2
+0+18 <[^>]*> fac1 f082 	crc32b	r0, r1, r2
+0+1c <[^>]*> fac1 f092 	crc32h	r0, r1, r2
+0+20 <[^>]*> fac1 f0a2 	crc32w	r0, r1, r2
+0+24 <[^>]*> fad1 f082 	crc32cb	r0, r1, r2
+0+28 <[^>]*> fad1 f092 	crc32ch	r0, r1, r2
+0+2c <[^>]*> fad1 f0a2 	crc32cw	r0, r1, r2
+
diff --git a/gas/testsuite/gas/arm/mask_1.d b/gas/testsuite/gas/arm/mask_1-armv8-a.d
index eddcd65..ece640a 100644
--- a/gas/testsuite/gas/arm/mask_1.d
+++ b/gas/testsuite/gas/arm/mask_1-armv8-a.d
@@ -1,5 +1,6 @@
 #objdump: -dr --prefix-address --show-raw-insn
-#name: vsel, vmaxnm, vminnm, vrint decoding mask.
+#name: ARMv8-A vsel, vmaxnm, vminnm, vrint decoding mask.
+#source: mask_1-armv8-ar.s
 #as: -march=armv8-a
 # This test is only valid on ELF based ports.
 #not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
diff --git a/gas/testsuite/gas/arm/mask_1.s b/gas/testsuite/gas/arm/mask_1-armv8-ar.s
index 7a347d8..7a347d8 100644
--- a/gas/testsuite/gas/arm/mask_1.s
+++ b/gas/testsuite/gas/arm/mask_1-armv8-ar.s
diff --git a/gas/testsuite/gas/arm/mask_1-armv8-r.d b/gas/testsuite/gas/arm/mask_1-armv8-r.d
new file mode 100644
index 0000000..6da82ef
--- /dev/null
+++ b/gas/testsuite/gas/arm/mask_1-armv8-r.d
@@ -0,0 +1,29 @@
+#objdump: -dr --prefix-address --show-raw-insn
+#name: ARMv8-R vsel, vmaxnm, vminnm, vrint decoding mask.
+#source: mask_1-armv8-ar.s
+#as: -march=armv8-r
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+# Test VFMA instruction disassembly
+
+.*: *file format .*arm.*
+
+
+Disassembly of section .text:
+0+000 <.*> fe011a10 	mcr2	10, 0, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
+0+004 <.*> fe011b10 	mcr2	11, 0, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
+0+008 <.*> fe811a10 	mcr2	10, 4, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
+0+00c <.*> fe811b10 	mcr2	11, 4, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
+0+010 <.*> fe811a50 	mcr2	10, 4, r1, cr1, cr0, \{2\}	; <UNPREDICTABLE>
+0+014 <.*> fe811b50 	mcr2	11, 4, r1, cr1, cr0, \{2\}	; <UNPREDICTABLE>
+0+018 <.*> fefb0ae0 			; <UNDEFINED> instruction: 0xfefb0ae0
+0+01c <.*> fefb0be0 			; <UNDEFINED> instruction: 0xfefb0be0
+0+020 <.*> fefb0ae0 			; <UNDEFINED> instruction: 0xfefb0ae0
+0+024 <.*> fefb0be0 			; <UNDEFINED> instruction: 0xfefb0be0
+0+028 <.*> fef80ae0 			; <UNDEFINED> instruction: 0xfef80ae0
+0+02c <.*> fef80be0 			; <UNDEFINED> instruction: 0xfef80be0
+0+030 <.*> fef90ae0 			; <UNDEFINED> instruction: 0xfef90ae0
+0+034 <.*> fef90be0 			; <UNDEFINED> instruction: 0xfef90be0
+0+038 <.*> fefa0ae0 			; <UNDEFINED> instruction: 0xfefa0ae0
+0+03c <.*> fefa0be0 			; <UNDEFINED> instruction: 0xfefa0be0
diff --git a/include/ChangeLog b/include/ChangeLog
index ec910a3..7df0bfa 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,16 @@
 2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
+	* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
+	* opcode/arm.h (ARM_EXT2_V8A): New macro.
+	(ARM_AEXT2_V8A): Rename into ...
+	(ARM_AEXT2_V8AR): This.
+	(ARM_AEXT2_V8A): New macro.
+	(ARM_AEXT_V8R): New macro.
+	(ARM_AEXT2_V8R): New macro.
+	(ARM_ARCH_V8R): New macro.
+
+2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
 	* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
 	(ARM_AEXT_V4T): Likewise.
 	(ARM_AEXT_V5TxM): Likewise.
diff --git a/include/elf/arm.h b/include/elf/arm.h
index 270aa45..30a31e6 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -106,6 +106,7 @@
 #define TAG_CPU_ARCH_V6S_M	12
 #define TAG_CPU_ARCH_V7E_M	13
 #define TAG_CPU_ARCH_V8		14
+#define TAG_CPU_ARCH_V8R	15
 #define TAG_CPU_ARCH_V8M_BASE	16
 #define TAG_CPU_ARCH_V8M_MAIN	17
 #define MAX_TAG_CPU_ARCH	TAG_CPU_ARCH_V8M_MAIN
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 62683a3..e2049a0 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -65,6 +65,7 @@
 #define ARM_EXT2_V8M_MAIN  0x00000040	/* ARMv8-M Mainline.  */
 #define ARM_EXT2_RAS	 0x00000080	/* RAS extension.  */
 #define ARM_EXT2_V8_3A	 0x00000100	/* ARM V8.3A.  */
+#define ARM_EXT2_V8A	 0x00000200	/* ARMv8-A.  */
 
 /* Co-processor space extensions.  */
 #define ARM_CEXT_XSCALE   0x00000001	/* Allow MIA etc.          */
@@ -149,7 +150,8 @@
 #define ARM_AEXT_V8A \
   (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
    | ARM_EXT_VIRT | ARM_EXT_V8)
-#define ARM_AEXT2_V8A	(ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS)
+#define ARM_AEXT2_V8AR	(ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS)
+#define ARM_AEXT2_V8A	(ARM_AEXT2_V8AR | ARM_EXT2_V8A)
 #define ARM_AEXT2_V8_1A	(ARM_AEXT2_V8A | ARM_EXT2_PAN)
 #define ARM_AEXT2_V8_2A	(ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS)
 #define ARM_AEXT2_V8_3A	(ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A)
@@ -159,6 +161,8 @@
 #define ARM_AEXT2_V8M	(ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M)
 #define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN)
 #define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN
+#define ARM_AEXT_V8R	ARM_AEXT_V8A
+#define ARM_AEXT2_V8R	ARM_AEXT2_V8AR
 
 /* Processors with specific extensions in the co-processor space.  */
 #define ARM_ARCH_XSCALE	ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
@@ -282,6 +286,7 @@
 					    ARM_AEXT2_V8M_MAIN)
 #define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \
 						ARM_AEXT2_V8M_MAIN_DSP)
+#define ARM_ARCH_V8R	ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R)
 
 /* Some useful combinations:  */
 #define ARM_ARCH_NONE	ARM_FEATURE_LOW (0, 0)