diff options
author | Alexandre Oliva <aoliva@redhat.com> | 2004-06-21 14:45:42 +0000 |
---|---|---|
committer | Alexandre Oliva <aoliva@redhat.com> | 2004-06-21 14:45:42 +0000 |
commit | aee6f5b4bd1c978694bede743979c0c4f560d46b (patch) | |
tree | a185bf850c2fe9563a1fbf0a89a5c6b981cddbe4 | |
parent | 05576f107c90440f15fa8a03e009c3f541af0b75 (diff) | |
download | binutils-aee6f5b4bd1c978694bede743979c0c4f560d46b.zip binutils-aee6f5b4bd1c978694bede743979c0c4f560d46b.tar.gz binutils-aee6f5b4bd1c978694bede743979c0c4f560d46b.tar.bz2 |
bfd/ChangeLog:
* elf-bfd.h (struct elf_backend_data): Added
elf_backend_omit_section_dynsym.
(_bfd_elf_link_omit_section_dynsym): Declare.
* elf32-frv.c (_frvfdpic_link_omit_section_dynsym): New.
(elf_backend_omit_section_dynsym): Use it for frvfdpic.
* elflink.c (_bfd_elf_link_omit_section_dynsym): Split out of...
(_bfd_elf_link_renumber_dynsyms): ... this function.
* elfxx-target.h (elf_backend_omit_section_dynsym): Default to
_bfd_elf_link_omit_section_dynsym).
(elfNN_bed): Added elf_backend_omit_section_dynsym.
ld/ChangeLog:
* emulparams/elf32frvfd.sh (GENERATE_PIE_SCRIPT): Set to yes.
ld/testsuite/ChangeLog:
* ld-frv/fdpic-pie-1.d: Adjust for pie-specific link script.
* ld-frv/fdpic-pie-2.d: Likewise.
* ld-frv/fdpic-pie-6.d: Likewise.
* ld-frv/fdpic-pie-7.d: Likewise.
* ld-frv/fdpic-pie-8.d: Likewise.
* ld-frv/fdpic-shared-1.d: Likewise.
* ld-frv/fdpic-shared-2.d: Likewise.
* ld-frv/fdpic-shared-3.d: Likewise.
* ld-frv/fdpic-shared-4.d: Likewise.
* ld-frv/fdpic-shared-5.d: Likewise.
* ld-frv/fdpic-shared-6.d: Likewise.
* ld-frv/fdpic-shared-7.d: Likewise.
* ld-frv/fdpic-shared-8.d: Likewise.
* ld-frv/fdpic-shared-local-2.d: Likewise.
* ld-frv/fdpic-shared-local-8.d: Likewise.
-rw-r--r-- | bfd/ChangeLog | 13 | ||||
-rw-r--r-- | bfd/elf-bfd.h | 7 | ||||
-rw-r--r-- | bfd/elf32-frv.c | 27 | ||||
-rw-r--r-- | bfd/elflink.c | 70 | ||||
-rw-r--r-- | bfd/elfxx-target.h | 4 | ||||
-rw-r--r-- | ld/ChangeLog | 4 | ||||
-rw-r--r-- | ld/emulparams/elf32frvfd.sh | 1 | ||||
-rw-r--r-- | ld/testsuite/ChangeLog | 18 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-pie-1.d | 82 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-pie-2.d | 108 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-pie-6.d | 110 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-pie-7.d | 82 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-pie-8.d | 108 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-1.d | 82 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-2.d | 120 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-3.d | 132 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-4.d | 108 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-5.d | 132 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-6.d | 110 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-7.d | 82 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-8.d | 132 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-local-2.d | 132 | ||||
-rw-r--r-- | ld/testsuite/ld-frv/fdpic-shared-local-8.d | 132 |
23 files changed, 941 insertions, 855 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 79c506e..ec5c63e 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,16 @@ +2004-06-21 Alexandre Oliva <aoliva@redhat.com> + + * elf-bfd.h (struct elf_backend_data): Added + elf_backend_omit_section_dynsym. + (_bfd_elf_link_omit_section_dynsym): Declare. + * elf32-frv.c (_frvfdpic_link_omit_section_dynsym): New. + (elf_backend_omit_section_dynsym): Use it for frvfdpic. + * elflink.c (_bfd_elf_link_omit_section_dynsym): Split out of... + (_bfd_elf_link_renumber_dynsyms): ... this function. + * elfxx-target.h (elf_backend_omit_section_dynsym): Default to + _bfd_elf_link_omit_section_dynsym). + (elfNN_bed): Added elf_backend_omit_section_dynsym. + 2004-06-21 Nick Clifton <nickc@redhat.com> * coffcode.h (styp_to_sec_flags): Ignore IMAGE_SCN_MEM_NOT_PAGED diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h index 220e401..e140c68 100644 --- a/bfd/elf-bfd.h +++ b/bfd/elf-bfd.h @@ -646,6 +646,11 @@ struct elf_backend_data bfd_boolean (*elf_backend_create_dynamic_sections) (bfd *abfd, struct bfd_link_info *info); + /* When creating a shared library, determine whether to omit the + dynamic symbol for the section. */ + bfd_boolean (*elf_backend_omit_section_dynsym) + (bfd *output_bfd, struct bfd_link_info *info, asection *osec); + /* The CHECK_RELOCS function is called by the add_symbols phase of the ELF backend linker. It is called once for each section with relocs of an object file, just after the symbols for the object @@ -1520,6 +1525,8 @@ extern bfd_boolean _bfd_elf_validate_reloc extern bfd_boolean _bfd_elf_link_create_dynamic_sections (bfd *, struct bfd_link_info *); +extern bfd_boolean _bfd_elf_link_omit_section_dynsym + (bfd *, struct bfd_link_info *, asection *); extern bfd_boolean _bfd_elf_create_dynamic_sections (bfd *, struct bfd_link_info *); extern bfd_boolean _bfd_elf_create_got_section diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c index cf3195a..ad2c324 100644 --- a/bfd/elf32-frv.c +++ b/bfd/elf32-frv.c @@ -2685,6 +2685,30 @@ elf32_frv_add_symbol_hook (abfd, info, sym, namep, flagsp, secp, valp) return TRUE; } +/* We need dynamic symbols for every section, since segments can + relocate independently. */ +static bfd_boolean +_frvfdpic_link_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info + ATTRIBUTE_UNUSED, + asection *p ATTRIBUTE_UNUSED) +{ + switch (elf_section_data (p)->this_hdr.sh_type) + { + case SHT_PROGBITS: + case SHT_NOBITS: + /* If sh_type is yet undecided, assume it could be + SHT_PROGBITS/SHT_NOBITS. */ + case SHT_NULL: + return FALSE; + + /* There shouldn't be section relative relocations + against any other section. */ + default: + return TRUE; + } +} + /* Create a .got section, as well as its additional info field. This is almost entirely copied from elflink.c:_bfd_elf_create_got_section(). */ @@ -4825,4 +4849,7 @@ frv_elf_print_private_bfd_data (abfd, ptr) #undef elf_backend_default_use_rela_p #define elf_backend_default_use_rela_p 1 +#undef elf_backend_omit_section_dynsym +#define elf_backend_omit_section_dynsym _frvfdpic_link_omit_section_dynsym + #include "elf32-target.h" diff --git a/bfd/elflink.c b/bfd/elflink.c index 37b113b..622d406 100644 --- a/bfd/elflink.c +++ b/bfd/elflink.c @@ -608,6 +608,43 @@ elf_link_renumber_hash_table_dynsyms (struct elf_link_hash_entry *h, return TRUE; } +/* Return true if the dynamic symbol for a given section should be + omitted when creating a shared library. */ +bfd_boolean +_bfd_elf_link_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info, + asection *p) +{ + switch (elf_section_data (p)->this_hdr.sh_type) + { + case SHT_PROGBITS: + case SHT_NOBITS: + /* If sh_type is yet undecided, assume it could be + SHT_PROGBITS/SHT_NOBITS. */ + case SHT_NULL: + if (strcmp (p->name, ".got") == 0 + || strcmp (p->name, ".got.plt") == 0 + || strcmp (p->name, ".plt") == 0) + { + asection *ip; + bfd *dynobj = elf_hash_table (info)->dynobj; + + if (dynobj != NULL + && (ip = bfd_get_section_by_name (dynobj, p->name)) + != NULL + && (ip->flags & SEC_LINKER_CREATED) + && ip->output_section == p) + return TRUE; + } + return FALSE; + + /* There shouldn't be section relative relocations + against any other section. */ + default: + return TRUE; + } +} + /* Assign dynsym indices. In a shared library we generate a section symbol for each output section, which come first. Next come all of the back-end allocated local dynamic syms, followed by the rest of @@ -620,38 +657,13 @@ _bfd_elf_link_renumber_dynsyms (bfd *output_bfd, struct bfd_link_info *info) if (info->shared) { + const struct elf_backend_data *bed = get_elf_backend_data (output_bfd); asection *p; for (p = output_bfd->sections; p ; p = p->next) if ((p->flags & SEC_EXCLUDE) == 0 - && (p->flags & SEC_ALLOC) != 0) - switch (elf_section_data (p)->this_hdr.sh_type) - { - case SHT_PROGBITS: - case SHT_NOBITS: - /* If sh_type is yet undecided, assume it could be - SHT_PROGBITS/SHT_NOBITS. */ - case SHT_NULL: - if (strcmp (p->name, ".got") == 0 - || strcmp (p->name, ".got.plt") == 0 - || strcmp (p->name, ".plt") == 0) - { - asection *ip; - bfd *dynobj = elf_hash_table (info)->dynobj; - - if (dynobj != NULL - && (ip = bfd_get_section_by_name (dynobj, p->name)) - != NULL - && (ip->flags & SEC_LINKER_CREATED) - && ip->output_section == p) - continue; - } - elf_section_data (p)->dynindx = ++dynsymcount; - break; - /* There shouldn't be section relative relocations - against any other section. */ - default: - break; - } + && (p->flags & SEC_ALLOC) != 0 + && !(*bed->elf_backend_omit_section_dynsym) (output_bfd, info, p)) + elf_section_data (p)->dynindx = ++dynsymcount; } if (elf_hash_table (info)->dynlocal) diff --git a/bfd/elfxx-target.h b/bfd/elfxx-target.h index d0773e5..af04ecb 100644 --- a/bfd/elfxx-target.h +++ b/bfd/elfxx-target.h @@ -324,6 +324,9 @@ #ifndef elf_backend_create_dynamic_sections #define elf_backend_create_dynamic_sections 0 #endif +#ifndef elf_backend_omit_section_dynsym +#define elf_backend_omit_section_dynsym _bfd_elf_link_omit_section_dynsym +#endif #ifndef elf_backend_check_relocs #define elf_backend_check_relocs 0 #endif @@ -505,6 +508,7 @@ static const struct elf_backend_data elfNN_bed = elf_backend_add_symbol_hook, elf_backend_link_output_symbol_hook, elf_backend_create_dynamic_sections, + elf_backend_omit_section_dynsym, elf_backend_check_relocs, elf_backend_adjust_dynamic_symbol, elf_backend_always_size_sections, diff --git a/ld/ChangeLog b/ld/ChangeLog index c785f25..07003df 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,7 @@ +2004-06-21 Alexandre Oliva <aoliva@redhat.com> + + * emulparams/elf32frvfd.sh (GENERATE_PIE_SCRIPT): Set to yes. + 2004-06-18 Adam Nemet <anemet@lnxw.com> * configure.in: Set EXTRA_SHLIB_EXTENSION to .a for LynxOS. diff --git a/ld/emulparams/elf32frvfd.sh b/ld/emulparams/elf32frvfd.sh index c496878..42b36f7 100644 --- a/ld/emulparams/elf32frvfd.sh +++ b/ld/emulparams/elf32frvfd.sh @@ -4,6 +4,7 @@ OUTPUT_FORMAT="elf32-frvfdpic" MAXPAGESIZE=0x4000 TEMPLATE_NAME=elf32 GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes EMBEDDED= # This gets us program headers mapped as part of the text segment. OTHER_GOT_SYMBOLS= OTHER_READONLY_SECTIONS=" diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index f825698..1f6e84d 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,21 @@ +2004-06-21 Alexandre Oliva <aoliva@redhat.com> + + * ld-frv/fdpic-pie-1.d: Adjust for pie-specific link script. + * ld-frv/fdpic-pie-2.d: Likewise. + * ld-frv/fdpic-pie-6.d: Likewise. + * ld-frv/fdpic-pie-7.d: Likewise. + * ld-frv/fdpic-pie-8.d: Likewise. + * ld-frv/fdpic-shared-1.d: Likewise. + * ld-frv/fdpic-shared-2.d: Likewise. + * ld-frv/fdpic-shared-3.d: Likewise. + * ld-frv/fdpic-shared-4.d: Likewise. + * ld-frv/fdpic-shared-5.d: Likewise. + * ld-frv/fdpic-shared-6.d: Likewise. + * ld-frv/fdpic-shared-7.d: Likewise. + * ld-frv/fdpic-shared-8.d: Likewise. + * ld-frv/fdpic-shared-local-2.d: Likewise. + * ld-frv/fdpic-shared-local-8.d: Likewise. + 2004-06-21 Nick Clifton <nickc@redhat.com> * ld-elf/frame.exp: Handle ports which do not support the --shared diff --git a/ld/testsuite/ld-frv/fdpic-pie-1.d b/ld/testsuite/ld-frv/fdpic-pie-1.d index 15d36ae..17901e8 100644 --- a/ld/testsuite/ld-frv/fdpic-pie-1.d +++ b/ld/testsuite/ld-frv/fdpic-pie-1.d @@ -8,51 +8,51 @@ Disassembly of section \.text: -000003d0 <F1>: - 3d0: 80 3c 00 01 call 3d4 <\.F0> - -000003d4 <\.F0>: - 3d4: 80 40 f0 0c addi gr15,12,gr0 - 3d8: 80 fc 00 0c setlos 0xc,gr0 - 3dc: 80 f4 00 0c setlo 0xc,gr0 - 3e0: 80 f8 00 00 sethi hi\(0x0\),gr0 - 3e4: 80 40 f0 10 addi gr15,16,gr0 - 3e8: 80 fc 00 10 setlos 0x10,gr0 - 3ec: 80 f4 00 10 setlo 0x10,gr0 - 3f0: 80 f8 00 00 sethi hi\(0x0\),gr0 - 3f4: 80 40 ff f8 addi gr15,-8,gr0 - 3f8: 80 fc ff f8 setlos 0xfffffff8,gr0 - 3fc: 80 f4 ff f8 setlo 0xfff8,gr0 - 400: 80 f8 ff ff sethi 0xffff,gr0 - 404: 80 40 ff 74 addi gr15,-140,gr0 - 408: 80 fc ff 74 setlos 0xffffff74,gr0 - 40c: 80 f4 ff 74 setlo 0xff74,gr0 - 410: 80 f8 ff ff sethi 0xffff,gr0 - 414: 80 f4 00 14 setlo 0x14,gr0 - 418: 80 f8 00 00 sethi hi\(0x0\),gr0 +00000340 <F1>: + 340: 80 3c 00 01 call 344 <\.F0> + +00000344 <\.F0>: + 344: 80 40 f0 0c addi gr15,12,gr0 + 348: 80 fc 00 0c setlos 0xc,gr0 + 34c: 80 f4 00 0c setlo 0xc,gr0 + 350: 80 f8 00 00 sethi hi\(0x0\),gr0 + 354: 80 40 f0 10 addi gr15,16,gr0 + 358: 80 fc 00 10 setlos 0x10,gr0 + 35c: 80 f4 00 10 setlo 0x10,gr0 + 360: 80 f8 00 00 sethi hi\(0x0\),gr0 + 364: 80 40 ff f8 addi gr15,-8,gr0 + 368: 80 fc ff f8 setlos 0xfffffff8,gr0 + 36c: 80 f4 ff f8 setlo 0xfff8,gr0 + 370: 80 f8 ff ff sethi 0xffff,gr0 + 374: 80 40 ff ec addi gr15,-20,gr0 + 378: 80 fc ff ec setlos 0xffffffec,gr0 + 37c: 80 f4 ff ec setlo 0xffec,gr0 + 380: 80 f8 ff ff sethi 0xffff,gr0 + 384: 80 f4 00 14 setlo 0x14,gr0 + 388: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004430 <D1>: - 4430: 00 00 00 04 add\.p gr0,gr4,gr0 - 4430: R_FRV_32 \.data +00004408 <D1>: + 4408: 00 00 00 04 add\.p gr0,gr4,gr0 + 4408: R_FRV_32 \.data -00004434 <\.D0>: - 4434: 00 00 00 00 add\.p gr0,gr0,gr0 - 4434: R_FRV_32 \.got - 4438: 00 00 00 04 add\.p gr0,gr4,gr0 - 4438: R_FRV_32 \.text +0000440c <\.D0>: + 440c: 00 00 00 00 add\.p gr0,gr0,gr0 + 440c: R_FRV_32 \.got + 4410: 00 00 00 04 add\.p gr0,gr4,gr0 + 4410: R_FRV_32 \.text Disassembly of section \.got: -000044b8 <_GLOBAL_OFFSET_TABLE_-0x8>: - 44b8: 00 00 00 04 add\.p gr0,gr4,gr0 - 44b8: R_FRV_FUNCDESC_VALUE \.text - 44bc: 00 00 00 02 add\.p gr0,fp,gr0 +00004418 <_GLOBAL_OFFSET_TABLE_-0x8>: + 4418: 00 00 00 04 add\.p gr0,gr4,gr0 + 4418: R_FRV_FUNCDESC_VALUE \.text + 441c: 00 00 00 02 add\.p gr0,fp,gr0 -000044c0 <_GLOBAL_OFFSET_TABLE_>: +00004420 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 44cc: 00 00 00 04 add\.p gr0,gr4,gr0 - 44cc: R_FRV_32 \.text - 44d0: 00 00 00 00 add\.p gr0,gr0,gr0 - 44d0: R_FRV_32 \.got - 44d4: 00 00 00 04 add\.p gr0,gr4,gr0 - 44d4: R_FRV_32 \.data + 442c: 00 00 00 04 add\.p gr0,gr4,gr0 + 442c: R_FRV_32 \.text + 4430: 00 00 00 00 add\.p gr0,gr0,gr0 + 4430: R_FRV_32 \.got + 4434: 00 00 00 04 add\.p gr0,gr4,gr0 + 4434: R_FRV_32 \.data diff --git a/ld/testsuite/ld-frv/fdpic-pie-2.d b/ld/testsuite/ld-frv/fdpic-pie-2.d index fb5e1e6..e03af40 100644 --- a/ld/testsuite/ld-frv/fdpic-pie-2.d +++ b/ld/testsuite/ld-frv/fdpic-pie-2.d @@ -8,65 +8,65 @@ Disassembly of section \.text: -000005d0 <F2>: - 5d0: 80 3c 00 01 call 5d4 <GF0> +000004f0 <F2>: + 4f0: 80 3c 00 01 call 4f4 <GF0> -000005d4 <GF0>: - 5d4: 80 40 f0 10 addi gr15,16,gr0 - 5d8: 80 fc 00 24 setlos 0x24,gr0 - 5dc: 80 f4 00 20 setlo 0x20,gr0 - 5e0: 80 f8 00 00 sethi hi\(0x0\),gr0 - 5e4: 80 40 f0 0c addi gr15,12,gr0 - 5e8: 80 fc 00 18 setlos 0x18,gr0 - 5ec: 80 f4 00 14 setlo 0x14,gr0 - 5f0: 80 f8 00 00 sethi hi\(0x0\),gr0 - 5f4: 80 40 ff f8 addi gr15,-8,gr0 - 5f8: 80 fc ff f0 setlos 0xfffffff0,gr0 - 5fc: 80 f4 ff e8 setlo 0xffe8,gr0 - 600: 80 f8 ff ff sethi 0xffff,gr0 - 604: 80 40 ff 64 addi gr15,-156,gr0 - 608: 80 fc ff 64 setlos 0xffffff64,gr0 - 60c: 80 f4 ff 64 setlo 0xff64,gr0 - 610: 80 f8 ff ff sethi 0xffff,gr0 - 614: 80 f4 00 1c setlo 0x1c,gr0 - 618: 80 f8 00 00 sethi hi\(0x0\),gr0 +000004f4 <GF0>: + 4f4: 80 40 f0 10 addi gr15,16,gr0 + 4f8: 80 fc 00 24 setlos 0x24,gr0 + 4fc: 80 f4 00 20 setlo 0x20,gr0 + 500: 80 f8 00 00 sethi hi\(0x0\),gr0 + 504: 80 40 f0 0c addi gr15,12,gr0 + 508: 80 fc 00 18 setlos 0x18,gr0 + 50c: 80 f4 00 14 setlo 0x14,gr0 + 510: 80 f8 00 00 sethi hi\(0x0\),gr0 + 514: 80 40 ff f8 addi gr15,-8,gr0 + 518: 80 fc ff f0 setlos 0xfffffff0,gr0 + 51c: 80 f4 ff e8 setlo 0xffe8,gr0 + 520: 80 f8 ff ff sethi 0xffff,gr0 + 524: 80 40 ff dc addi gr15,-36,gr0 + 528: 80 fc ff dc setlos 0xffffffdc,gr0 + 52c: 80 f4 ff dc setlo 0xffdc,gr0 + 530: 80 f8 ff ff sethi 0xffff,gr0 + 534: 80 f4 00 1c setlo 0x1c,gr0 + 538: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004630 <D2>: - 4630: 00 00 00 04 add\.p gr0,gr4,gr0 - 4630: R_FRV_32 \.data +000045b8 <D2>: + 45b8: 00 00 00 04 add\.p gr0,gr4,gr0 + 45b8: R_FRV_32 \.data -00004634 <GD0>: - 4634: 00 00 00 04 add\.p gr0,gr4,gr0 - 4634: R_FRV_FUNCDESC \.text - 4638: 00 00 00 04 add\.p gr0,gr4,gr0 - 4638: R_FRV_32 \.text +000045bc <GD0>: + 45bc: 00 00 00 04 add\.p gr0,gr4,gr0 + 45bc: R_FRV_FUNCDESC \.text + 45c0: 00 00 00 04 add\.p gr0,gr4,gr0 + 45c0: R_FRV_32 \.text Disassembly of section \.got: -000046b8 <_GLOBAL_OFFSET_TABLE_-0x18>: - 46b8: 00 00 00 04 add\.p gr0,gr4,gr0 - 46b8: R_FRV_FUNCDESC_VALUE \.text - 46bc: 00 00 00 02 add\.p gr0,fp,gr0 - 46c0: 00 00 00 04 add\.p gr0,gr4,gr0 - 46c0: R_FRV_FUNCDESC_VALUE \.text - 46c4: 00 00 00 02 add\.p gr0,fp,gr0 - 46c8: 00 00 00 04 add\.p gr0,gr4,gr0 - 46c8: R_FRV_FUNCDESC_VALUE \.text - 46cc: 00 00 00 02 add\.p gr0,fp,gr0 +000045c8 <_GLOBAL_OFFSET_TABLE_-0x18>: + 45c8: 00 00 00 04 add\.p gr0,gr4,gr0 + 45c8: R_FRV_FUNCDESC_VALUE \.text + 45cc: 00 00 00 02 add\.p gr0,fp,gr0 + 45d0: 00 00 00 04 add\.p gr0,gr4,gr0 + 45d0: R_FRV_FUNCDESC_VALUE \.text + 45d4: 00 00 00 02 add\.p gr0,fp,gr0 + 45d8: 00 00 00 04 add\.p gr0,gr4,gr0 + 45d8: R_FRV_FUNCDESC_VALUE \.text + 45dc: 00 00 00 02 add\.p gr0,fp,gr0 -000046d0 <_GLOBAL_OFFSET_TABLE_>: +000045e0 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 46dc: 00 00 00 04 add\.p gr0,gr4,gr0 - 46dc: R_FRV_FUNCDESC \.text - 46e0: 00 00 00 04 add\.p gr0,gr4,gr0 - 46e0: R_FRV_32 \.text - 46e4: 00 00 00 04 add\.p gr0,gr4,gr0 - 46e4: R_FRV_FUNCDESC \.text - 46e8: 00 00 00 04 add\.p gr0,gr4,gr0 - 46e8: R_FRV_FUNCDESC \.text - 46ec: 00 00 00 04 add\.p gr0,gr4,gr0 - 46ec: R_FRV_32 \.data - 46f0: 00 00 00 04 add\.p gr0,gr4,gr0 - 46f0: R_FRV_32 \.text - 46f4: 00 00 00 04 add\.p gr0,gr4,gr0 - 46f4: R_FRV_32 \.text + 45ec: 00 00 00 04 add\.p gr0,gr4,gr0 + 45ec: R_FRV_FUNCDESC \.text + 45f0: 00 00 00 04 add\.p gr0,gr4,gr0 + 45f0: R_FRV_32 \.text + 45f4: 00 00 00 04 add\.p gr0,gr4,gr0 + 45f4: R_FRV_FUNCDESC \.text + 45f8: 00 00 00 04 add\.p gr0,gr4,gr0 + 45f8: R_FRV_FUNCDESC \.text + 45fc: 00 00 00 04 add\.p gr0,gr4,gr0 + 45fc: R_FRV_32 \.data + 4600: 00 00 00 04 add\.p gr0,gr4,gr0 + 4600: R_FRV_32 \.text + 4604: 00 00 00 04 add\.p gr0,gr4,gr0 + 4604: R_FRV_32 \.text diff --git a/ld/testsuite/ld-frv/fdpic-pie-6.d b/ld/testsuite/ld-frv/fdpic-pie-6.d index c9263f7..9ad328b 100644 --- a/ld/testsuite/ld-frv/fdpic-pie-6.d +++ b/ld/testsuite/ld-frv/fdpic-pie-6.d @@ -8,67 +8,67 @@ Disassembly of section \.plt: -000005a8 <\.plt>: - 5a8: 00 00 00 08 add\.p gr0,gr8,gr0 - 5ac: c0 1a 00 06 bra 5c4 <F6-0x10> - 5b0: 00 00 00 00 add\.p gr0,gr0,gr0 - 5b4: c0 1a 00 04 bra 5c4 <F6-0x10> - 5b8: 00 00 00 10 add\.p gr0,gr16,gr0 - 5bc: c0 1a 00 02 bra 5c4 <F6-0x10> - 5c0: 00 00 00 18 add\.p gr0,gr24,gr0 - 5c4: 88 08 f1 40 ldd @\(gr15,gr0\),gr4 - 5c8: 80 30 40 00 jmpl @\(gr4,gr0\) - 5cc: 9c cc ff f0 lddi @\(gr15,-16\),gr14 - 5d0: 80 30 e0 00 jmpl @\(gr14,gr0\) +000004c8 <\.plt>: + 4c8: 00 00 00 08 add\.p gr0,gr8,gr0 + 4cc: c0 1a 00 06 bra 4e4 <F6-0x10> + 4d0: 00 00 00 00 add\.p gr0,gr0,gr0 + 4d4: c0 1a 00 04 bra 4e4 <F6-0x10> + 4d8: 00 00 00 10 add\.p gr0,gr16,gr0 + 4dc: c0 1a 00 02 bra 4e4 <F6-0x10> + 4e0: 00 00 00 18 add\.p gr0,gr24,gr0 + 4e4: 88 08 f1 40 ldd @\(gr15,gr0\),gr4 + 4e8: 80 30 40 00 jmpl @\(gr4,gr0\) + 4ec: 9c cc ff f0 lddi @\(gr15,-16\),gr14 + 4f0: 80 30 e0 00 jmpl @\(gr14,gr0\) Disassembly of section \.text: -000005d4 <F6>: - 5d4: fe 3f ff fe call 5cc <F6-0x8> - 5d8: 80 40 f0 0c addi gr15,12,gr0 - 5dc: 80 fc 00 24 setlos 0x24,gr0 - 5e0: 80 f4 00 20 setlo 0x20,gr0 - 5e4: 80 f8 00 00 sethi hi\(0x0\),gr0 - 5e8: 80 40 f0 10 addi gr15,16,gr0 - 5ec: 80 fc 00 18 setlos 0x18,gr0 - 5f0: 80 f4 00 1c setlo 0x1c,gr0 - 5f4: 80 f8 00 00 sethi hi\(0x0\),gr0 - 5f8: 80 40 ff f8 addi gr15,-8,gr0 - 5fc: 80 fc ff e8 setlos 0xffffffe8,gr0 - 600: 80 f4 ff e0 setlo 0xffe0,gr0 - 604: 80 f8 ff ff sethi 0xffff,gr0 - 608: 80 f4 ff 44 setlo 0xff44,gr0 - 60c: 80 f8 ff ff sethi 0xffff,gr0 - 610: 80 f4 00 14 setlo 0x14,gr0 - 614: 80 f8 00 00 sethi hi\(0x0\),gr0 +000004f4 <F6>: + 4f4: fe 3f ff fe call 4ec <F6-0x8> + 4f8: 80 40 f0 0c addi gr15,12,gr0 + 4fc: 80 fc 00 24 setlos 0x24,gr0 + 500: 80 f4 00 20 setlo 0x20,gr0 + 504: 80 f8 00 00 sethi hi\(0x0\),gr0 + 508: 80 40 f0 10 addi gr15,16,gr0 + 50c: 80 fc 00 18 setlos 0x18,gr0 + 510: 80 f4 00 1c setlo 0x1c,gr0 + 514: 80 f8 00 00 sethi hi\(0x0\),gr0 + 518: 80 40 ff f8 addi gr15,-8,gr0 + 51c: 80 fc ff e8 setlos 0xffffffe8,gr0 + 520: 80 f4 ff e0 setlo 0xffe0,gr0 + 524: 80 f8 ff ff sethi 0xffff,gr0 + 528: 80 f4 ff d4 setlo 0xffd4,gr0 + 52c: 80 f8 ff ff sethi 0xffff,gr0 + 530: 80 f4 00 14 setlo 0x14,gr0 + 534: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -0000462c <D6>: +000045cc <D6>: \.\.\. - 462c: R_FRV_32 WD0 - 4630: R_FRV_FUNCDESC WFb - 4634: R_FRV_32 WFb + 45cc: R_FRV_32 WD0 + 45d0: R_FRV_FUNCDESC WFb + 45d4: R_FRV_32 WFb Disassembly of section \.got: -000046c8 <_GLOBAL_OFFSET_TABLE_-0x20>: - 46c8: 00 00 05 c4 subxcc\.p gr0,gr4,gr0,icc1 - 46c8: R_FRV_FUNCDESC_VALUE WF9 - 46cc: 00 00 00 02 add\.p gr0,fp,gr0 - 46d0: 00 00 05 bc subx\.p gr0,gr60,gr0,icc1 - 46d0: R_FRV_FUNCDESC_VALUE WF8 - 46d4: 00 00 00 02 add\.p gr0,fp,gr0 - 46d8: 00 00 05 b4 subx\.p gr0,gr52,gr0,icc1 - 46d8: R_FRV_FUNCDESC_VALUE WF0 - 46dc: 00 00 00 02 add\.p gr0,fp,gr0 - 46e0: 00 00 05 ac subx\.p gr0,gr44,gr0,icc1 - 46e0: R_FRV_FUNCDESC_VALUE WF7 - 46e4: 00 00 00 02 add\.p gr0,fp,gr0 +000045d8 <_GLOBAL_OFFSET_TABLE_-0x20>: + 45d8: 00 00 04 e4 addxcc\.p gr0,gr36,gr0,icc1 + 45d8: R_FRV_FUNCDESC_VALUE WF9 + 45dc: 00 00 00 02 add\.p gr0,fp,gr0 + 45e0: 00 00 04 dc addxcc\.p gr0,gr28,gr0,icc1 + 45e0: R_FRV_FUNCDESC_VALUE WF8 + 45e4: 00 00 00 02 add\.p gr0,fp,gr0 + 45e8: 00 00 04 d4 addxcc\.p gr0,gr20,gr0,icc1 + 45e8: R_FRV_FUNCDESC_VALUE WF0 + 45ec: 00 00 00 02 add\.p gr0,fp,gr0 + 45f0: 00 00 04 cc addxcc\.p gr0,gr12,gr0,icc1 + 45f0: R_FRV_FUNCDESC_VALUE WF7 + 45f4: 00 00 00 02 add\.p gr0,fp,gr0 -000046e8 <_GLOBAL_OFFSET_TABLE_>: +000045f8 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 46f4: R_FRV_32 WF1 - 46f8: R_FRV_FUNCDESC WF4 - 46fc: R_FRV_32 WD2 - 4700: R_FRV_FUNCDESC WF5 - 4704: R_FRV_FUNCDESC WF6 - 4708: R_FRV_32 WF3 - 470c: R_FRV_32 WF2 + 4604: R_FRV_32 WF1 + 4608: R_FRV_FUNCDESC WF4 + 460c: R_FRV_32 WD2 + 4610: R_FRV_FUNCDESC WF5 + 4614: R_FRV_FUNCDESC WF6 + 4618: R_FRV_32 WF3 + 461c: R_FRV_32 WF2 diff --git a/ld/testsuite/ld-frv/fdpic-pie-7.d b/ld/testsuite/ld-frv/fdpic-pie-7.d index 67a6abf..8448e5d 100644 --- a/ld/testsuite/ld-frv/fdpic-pie-7.d +++ b/ld/testsuite/ld-frv/fdpic-pie-7.d @@ -8,51 +8,51 @@ Disassembly of section \.text: -000003d0 <F7>: - 3d0: 80 3c 00 02 call 3d8 <\.F0\+0x4> - -000003d4 <\.F0>: - 3d4: 80 40 f0 0c addi gr15,12,gr0 - 3d8: 80 fc 00 0c setlos 0xc,gr0 - 3dc: 80 f4 00 0c setlo 0xc,gr0 - 3e0: 80 f8 00 00 sethi hi\(0x0\),gr0 - 3e4: 80 40 f0 10 addi gr15,16,gr0 - 3e8: 80 fc 00 10 setlos 0x10,gr0 - 3ec: 80 f4 00 10 setlo 0x10,gr0 - 3f0: 80 f8 00 00 sethi hi\(0x0\),gr0 - 3f4: 80 40 ff f8 addi gr15,-8,gr0 - 3f8: 80 fc ff f8 setlos 0xfffffff8,gr0 - 3fc: 80 f4 ff f8 setlo 0xfff8,gr0 - 400: 80 f8 ff ff sethi 0xffff,gr0 - 404: 80 40 ff 78 addi gr15,-136,gr0 - 408: 80 fc ff 78 setlos 0xffffff78,gr0 - 40c: 80 f4 ff 78 setlo 0xff78,gr0 - 410: 80 f8 ff ff sethi 0xffff,gr0 - 414: 80 f4 00 14 setlo 0x14,gr0 - 418: 80 f8 00 00 sethi hi\(0x0\),gr0 +00000340 <F7>: + 340: 80 3c 00 02 call 348 <\.F0\+0x4> + +00000344 <\.F0>: + 344: 80 40 f0 0c addi gr15,12,gr0 + 348: 80 fc 00 0c setlos 0xc,gr0 + 34c: 80 f4 00 0c setlo 0xc,gr0 + 350: 80 f8 00 00 sethi hi\(0x0\),gr0 + 354: 80 40 f0 10 addi gr15,16,gr0 + 358: 80 fc 00 10 setlos 0x10,gr0 + 35c: 80 f4 00 10 setlo 0x10,gr0 + 360: 80 f8 00 00 sethi hi\(0x0\),gr0 + 364: 80 40 ff f8 addi gr15,-8,gr0 + 368: 80 fc ff f8 setlos 0xfffffff8,gr0 + 36c: 80 f4 ff f8 setlo 0xfff8,gr0 + 370: 80 f8 ff ff sethi 0xffff,gr0 + 374: 80 40 ff f0 addi gr15,-16,gr0 + 378: 80 fc ff f0 setlos 0xfffffff0,gr0 + 37c: 80 f4 ff f0 setlo 0xfff0,gr0 + 380: 80 f8 ff ff sethi 0xffff,gr0 + 384: 80 f4 00 14 setlo 0x14,gr0 + 388: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004430 <D7>: - 4430: 00 00 00 08 add\.p gr0,gr8,gr0 - 4430: R_FRV_32 \.data +00004408 <D7>: + 4408: 00 00 00 08 add\.p gr0,gr8,gr0 + 4408: R_FRV_32 \.data -00004434 <\.D0>: - 4434: 00 00 00 00 add\.p gr0,gr0,gr0 - 4434: R_FRV_32 \.got - 4438: 00 00 00 08 add\.p gr0,gr8,gr0 - 4438: R_FRV_32 \.text +0000440c <\.D0>: + 440c: 00 00 00 00 add\.p gr0,gr0,gr0 + 440c: R_FRV_32 \.got + 4410: 00 00 00 08 add\.p gr0,gr8,gr0 + 4410: R_FRV_32 \.text Disassembly of section \.got: -000044b8 <_GLOBAL_OFFSET_TABLE_-0x8>: - 44b8: 00 00 00 08 add\.p gr0,gr8,gr0 - 44b8: R_FRV_FUNCDESC_VALUE \.text - 44bc: 00 00 00 02 add\.p gr0,fp,gr0 +00004418 <_GLOBAL_OFFSET_TABLE_-0x8>: + 4418: 00 00 00 08 add\.p gr0,gr8,gr0 + 4418: R_FRV_FUNCDESC_VALUE \.text + 441c: 00 00 00 02 add\.p gr0,fp,gr0 -000044c0 <_GLOBAL_OFFSET_TABLE_>: +00004420 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 44cc: 00 00 00 08 add\.p gr0,gr8,gr0 - 44cc: R_FRV_32 \.text - 44d0: 00 00 00 00 add\.p gr0,gr0,gr0 - 44d0: R_FRV_32 \.got - 44d4: 00 00 00 08 add\.p gr0,gr8,gr0 - 44d4: R_FRV_32 \.data + 442c: 00 00 00 08 add\.p gr0,gr8,gr0 + 442c: R_FRV_32 \.text + 4430: 00 00 00 00 add\.p gr0,gr0,gr0 + 4430: R_FRV_32 \.got + 4434: 00 00 00 08 add\.p gr0,gr8,gr0 + 4434: R_FRV_32 \.data diff --git a/ld/testsuite/ld-frv/fdpic-pie-8.d b/ld/testsuite/ld-frv/fdpic-pie-8.d index 20b0ea0..85437aa 100644 --- a/ld/testsuite/ld-frv/fdpic-pie-8.d +++ b/ld/testsuite/ld-frv/fdpic-pie-8.d @@ -8,65 +8,65 @@ Disassembly of section \.text: -000005d0 <F8>: - 5d0: 80 3c 00 02 call 5d8 <GF0\+0x4> +000004f0 <F8>: + 4f0: 80 3c 00 02 call 4f8 <GF0\+0x4> -000005d4 <GF0>: - 5d4: 80 40 f0 10 addi gr15,16,gr0 - 5d8: 80 fc 00 14 setlos 0x14,gr0 - 5dc: 80 f4 00 24 setlo 0x24,gr0 - 5e0: 80 f8 00 00 sethi hi\(0x0\),gr0 - 5e4: 80 40 f0 0c addi gr15,12,gr0 - 5e8: 80 fc 00 1c setlos 0x1c,gr0 - 5ec: 80 f4 00 18 setlo 0x18,gr0 - 5f0: 80 f8 00 00 sethi hi\(0x0\),gr0 - 5f4: 80 40 ff f8 addi gr15,-8,gr0 - 5f8: 80 fc ff f0 setlos 0xfffffff0,gr0 - 5fc: 80 f4 ff e8 setlo 0xffe8,gr0 - 600: 80 f8 ff ff sethi 0xffff,gr0 - 604: 80 40 ff 68 addi gr15,-152,gr0 - 608: 80 fc ff 68 setlos 0xffffff68,gr0 - 60c: 80 f4 ff 68 setlo 0xff68,gr0 - 610: 80 f8 ff ff sethi 0xffff,gr0 - 614: 80 f4 00 20 setlo 0x20,gr0 - 618: 80 f8 00 00 sethi hi\(0x0\),gr0 +000004f4 <GF0>: + 4f4: 80 40 f0 10 addi gr15,16,gr0 + 4f8: 80 fc 00 14 setlos 0x14,gr0 + 4fc: 80 f4 00 24 setlo 0x24,gr0 + 500: 80 f8 00 00 sethi hi\(0x0\),gr0 + 504: 80 40 f0 0c addi gr15,12,gr0 + 508: 80 fc 00 1c setlos 0x1c,gr0 + 50c: 80 f4 00 18 setlo 0x18,gr0 + 510: 80 f8 00 00 sethi hi\(0x0\),gr0 + 514: 80 40 ff f8 addi gr15,-8,gr0 + 518: 80 fc ff f0 setlos 0xfffffff0,gr0 + 51c: 80 f4 ff e8 setlo 0xffe8,gr0 + 520: 80 f8 ff ff sethi 0xffff,gr0 + 524: 80 40 ff e0 addi gr15,-32,gr0 + 528: 80 fc ff e0 setlos 0xffffffe0,gr0 + 52c: 80 f4 ff e0 setlo 0xffe0,gr0 + 530: 80 f8 ff ff sethi 0xffff,gr0 + 534: 80 f4 00 20 setlo 0x20,gr0 + 538: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004630 <D8>: - 4630: 00 00 00 08 add\.p gr0,gr8,gr0 - 4630: R_FRV_32 \.data +000045b8 <D8>: + 45b8: 00 00 00 08 add\.p gr0,gr8,gr0 + 45b8: R_FRV_32 \.data -00004634 <GD0>: - 4634: 00 00 00 08 add\.p gr0,gr8,gr0 - 4634: R_FRV_FUNCDESC \.text - 4638: 00 00 00 08 add\.p gr0,gr8,gr0 - 4638: R_FRV_32 \.text +000045bc <GD0>: + 45bc: 00 00 00 08 add\.p gr0,gr8,gr0 + 45bc: R_FRV_FUNCDESC \.text + 45c0: 00 00 00 08 add\.p gr0,gr8,gr0 + 45c0: R_FRV_32 \.text Disassembly of section \.got: -000046b8 <_GLOBAL_OFFSET_TABLE_-0x18>: - 46b8: 00 00 00 08 add\.p gr0,gr8,gr0 - 46b8: R_FRV_FUNCDESC_VALUE \.text - 46bc: 00 00 00 02 add\.p gr0,fp,gr0 - 46c0: 00 00 00 08 add\.p gr0,gr8,gr0 - 46c0: R_FRV_FUNCDESC_VALUE \.text - 46c4: 00 00 00 02 add\.p gr0,fp,gr0 - 46c8: 00 00 00 08 add\.p gr0,gr8,gr0 - 46c8: R_FRV_FUNCDESC_VALUE \.text - 46cc: 00 00 00 02 add\.p gr0,fp,gr0 +000045c8 <_GLOBAL_OFFSET_TABLE_-0x18>: + 45c8: 00 00 00 08 add\.p gr0,gr8,gr0 + 45c8: R_FRV_FUNCDESC_VALUE \.text + 45cc: 00 00 00 02 add\.p gr0,fp,gr0 + 45d0: 00 00 00 08 add\.p gr0,gr8,gr0 + 45d0: R_FRV_FUNCDESC_VALUE \.text + 45d4: 00 00 00 02 add\.p gr0,fp,gr0 + 45d8: 00 00 00 08 add\.p gr0,gr8,gr0 + 45d8: R_FRV_FUNCDESC_VALUE \.text + 45dc: 00 00 00 02 add\.p gr0,fp,gr0 -000046d0 <_GLOBAL_OFFSET_TABLE_>: +000045e0 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 46dc: 00 00 00 04 add\.p gr0,gr4,gr0 - 46dc: R_FRV_FUNCDESC \.text - 46e0: 00 00 00 08 add\.p gr0,gr8,gr0 - 46e0: R_FRV_32 \.text - 46e4: 00 00 00 08 add\.p gr0,gr8,gr0 - 46e4: R_FRV_32 \.text - 46e8: 00 00 00 04 add\.p gr0,gr4,gr0 - 46e8: R_FRV_FUNCDESC \.text - 46ec: 00 00 00 04 add\.p gr0,gr4,gr0 - 46ec: R_FRV_FUNCDESC \.text - 46f0: 00 00 00 08 add\.p gr0,gr8,gr0 - 46f0: R_FRV_32 \.data - 46f4: 00 00 00 08 add\.p gr0,gr8,gr0 - 46f4: R_FRV_32 \.text + 45ec: 00 00 00 04 add\.p gr0,gr4,gr0 + 45ec: R_FRV_FUNCDESC \.text + 45f0: 00 00 00 08 add\.p gr0,gr8,gr0 + 45f0: R_FRV_32 \.text + 45f4: 00 00 00 08 add\.p gr0,gr8,gr0 + 45f4: R_FRV_32 \.text + 45f8: 00 00 00 04 add\.p gr0,gr4,gr0 + 45f8: R_FRV_FUNCDESC \.text + 45fc: 00 00 00 04 add\.p gr0,gr4,gr0 + 45fc: R_FRV_FUNCDESC \.text + 4600: 00 00 00 08 add\.p gr0,gr8,gr0 + 4600: R_FRV_32 \.data + 4604: 00 00 00 08 add\.p gr0,gr8,gr0 + 4604: R_FRV_32 \.text diff --git a/ld/testsuite/ld-frv/fdpic-shared-1.d b/ld/testsuite/ld-frv/fdpic-shared-1.d index f0c5ce8..ad5cbc4 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-1.d +++ b/ld/testsuite/ld-frv/fdpic-shared-1.d @@ -8,51 +8,51 @@ Disassembly of section \.text: -000003dc <F1>: - 3dc: 80 3c 00 01 call 3e0 <\.F0> - -000003e0 <\.F0>: - 3e0: 80 40 f0 0c addi gr15,12,gr0 - 3e4: 80 fc 00 0c setlos 0xc,gr0 - 3e8: 80 f4 00 0c setlo 0xc,gr0 - 3ec: 80 f8 00 00 sethi hi\(0x0\),gr0 - 3f0: 80 40 f0 10 addi gr15,16,gr0 - 3f4: 80 fc 00 10 setlos 0x10,gr0 - 3f8: 80 f4 00 10 setlo 0x10,gr0 - 3fc: 80 f8 00 00 sethi hi\(0x0\),gr0 - 400: 80 40 ff f8 addi gr15,-8,gr0 - 404: 80 fc ff f8 setlos 0xfffffff8,gr0 - 408: 80 f4 ff f8 setlo 0xfff8,gr0 - 40c: 80 f8 ff ff sethi 0xffff,gr0 - 410: 80 40 ff 78 addi gr15,-136,gr0 - 414: 80 fc ff 78 setlos 0xffffff78,gr0 - 418: 80 f4 ff 78 setlo 0xff78,gr0 - 41c: 80 f8 ff ff sethi 0xffff,gr0 - 420: 80 f4 00 14 setlo 0x14,gr0 - 424: 80 f8 00 00 sethi hi\(0x0\),gr0 +0000033c <F1>: + 33c: 80 3c 00 01 call 340 <\.F0> + +00000340 <\.F0>: + 340: 80 40 f0 0c addi gr15,12,gr0 + 344: 80 fc 00 0c setlos 0xc,gr0 + 348: 80 f4 00 0c setlo 0xc,gr0 + 34c: 80 f8 00 00 sethi hi\(0x0\),gr0 + 350: 80 40 f0 10 addi gr15,16,gr0 + 354: 80 fc 00 10 setlos 0x10,gr0 + 358: 80 f4 00 10 setlo 0x10,gr0 + 35c: 80 f8 00 00 sethi hi\(0x0\),gr0 + 360: 80 40 ff f8 addi gr15,-8,gr0 + 364: 80 fc ff f8 setlos 0xfffffff8,gr0 + 368: 80 f4 ff f8 setlo 0xfff8,gr0 + 36c: 80 f8 ff ff sethi 0xffff,gr0 + 370: 80 40 ff f0 addi gr15,-16,gr0 + 374: 80 fc ff f0 setlos 0xfffffff0,gr0 + 378: 80 f4 ff f0 setlo 0xfff0,gr0 + 37c: 80 f8 ff ff sethi 0xffff,gr0 + 380: 80 f4 00 14 setlo 0x14,gr0 + 384: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -0000442c <D1>: - 442c: 00 00 00 04 add\.p gr0,gr4,gr0 - 442c: R_FRV_32 \.data +00004404 <D1>: + 4404: 00 00 00 04 add\.p gr0,gr4,gr0 + 4404: R_FRV_32 \.data -00004430 <\.D0>: - 4430: 00 00 00 00 add\.p gr0,gr0,gr0 - 4430: R_FRV_32 \.got - 4434: 00 00 00 04 add\.p gr0,gr4,gr0 - 4434: R_FRV_32 \.text +00004408 <\.D0>: + 4408: 00 00 00 00 add\.p gr0,gr0,gr0 + 4408: R_FRV_32 \.got + 440c: 00 00 00 04 add\.p gr0,gr4,gr0 + 440c: R_FRV_32 \.text Disassembly of section \.got: -000044b0 <_GLOBAL_OFFSET_TABLE_-0x8>: - 44b0: 00 00 00 04 add\.p gr0,gr4,gr0 - 44b0: R_FRV_FUNCDESC_VALUE \.text - 44b4: 00 00 00 00 add\.p gr0,gr0,gr0 +00004410 <_GLOBAL_OFFSET_TABLE_-0x8>: + 4410: 00 00 00 04 add\.p gr0,gr4,gr0 + 4410: R_FRV_FUNCDESC_VALUE \.text + 4414: 00 00 00 00 add\.p gr0,gr0,gr0 -000044b8 <_GLOBAL_OFFSET_TABLE_>: +00004418 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 44c4: 00 00 00 04 add\.p gr0,gr4,gr0 - 44c4: R_FRV_32 \.text - 44c8: 00 00 00 00 add\.p gr0,gr0,gr0 - 44c8: R_FRV_32 \.got - 44cc: 00 00 00 04 add\.p gr0,gr4,gr0 - 44cc: R_FRV_32 \.data + 4424: 00 00 00 04 add\.p gr0,gr4,gr0 + 4424: R_FRV_32 \.text + 4428: 00 00 00 00 add\.p gr0,gr0,gr0 + 4428: R_FRV_32 \.got + 442c: 00 00 00 04 add\.p gr0,gr4,gr0 + 442c: R_FRV_32 \.data diff --git a/ld/testsuite/ld-frv/fdpic-shared-2.d b/ld/testsuite/ld-frv/fdpic-shared-2.d index 04b7f98..6cc589f 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-2.d +++ b/ld/testsuite/ld-frv/fdpic-shared-2.d @@ -8,74 +8,74 @@ Disassembly of section \.plt: -000005c8 <\.plt>: - 5c8: 00 00 00 00 add\.p gr0,gr0,gr0 - 5cc: c0 1a 00 06 bra 5e4 <F2-0x10> - 5d0: 00 00 00 10 add\.p gr0,gr16,gr0 - 5d4: c0 1a 00 04 bra 5e4 <F2-0x10> - 5d8: 00 00 00 18 add\.p gr0,gr24,gr0 - 5dc: c0 1a 00 02 bra 5e4 <F2-0x10> - 5e0: 00 00 00 08 add\.p gr0,gr8,gr0 - 5e4: 88 08 f1 40 ldd @\(gr15,gr0\),gr4 - 5e8: 80 30 40 00 jmpl @\(gr4,gr0\) - 5ec: 9c cc ff f8 lddi @\(gr15,-8\),gr14 - 5f0: 80 30 e0 00 jmpl @\(gr14,gr0\) +000004d8 <\.plt>: + 4d8: 00 00 00 00 add\.p gr0,gr0,gr0 + 4dc: c0 1a 00 06 bra 4f4 <F2-0x10> + 4e0: 00 00 00 10 add\.p gr0,gr16,gr0 + 4e4: c0 1a 00 04 bra 4f4 <F2-0x10> + 4e8: 00 00 00 18 add\.p gr0,gr24,gr0 + 4ec: c0 1a 00 02 bra 4f4 <F2-0x10> + 4f0: 00 00 00 08 add\.p gr0,gr8,gr0 + 4f4: 88 08 f1 40 ldd @\(gr15,gr0\),gr4 + 4f8: 80 30 40 00 jmpl @\(gr4,gr0\) + 4fc: 9c cc ff f8 lddi @\(gr15,-8\),gr14 + 500: 80 30 e0 00 jmpl @\(gr14,gr0\) Disassembly of section \.text: -000005f4 <F2>: - 5f4: fe 3f ff fe call 5ec <F2-0x8> +00000504 <F2>: + 504: fe 3f ff fe call 4fc <F2-0x8> -000005f8 <GF0>: - 5f8: 80 40 f0 10 addi gr15,16,gr0 - 5fc: 80 fc 00 24 setlos 0x24,gr0 - 600: 80 f4 00 20 setlo 0x20,gr0 - 604: 80 f8 00 00 sethi hi\(0x0\),gr0 - 608: 80 40 f0 0c addi gr15,12,gr0 - 60c: 80 fc 00 18 setlos 0x18,gr0 - 610: 80 f4 00 14 setlo 0x14,gr0 - 614: 80 f8 00 00 sethi hi\(0x0\),gr0 - 618: 80 40 ff f0 addi gr15,-16,gr0 - 61c: 80 fc ff e8 setlos 0xffffffe8,gr0 - 620: 80 f4 ff e0 setlo 0xffe0,gr0 - 624: 80 f8 ff ff sethi 0xffff,gr0 - 628: 80 40 ff 48 addi gr15,-184,gr0 - 62c: 80 fc ff 48 setlos 0xffffff48,gr0 - 630: 80 f4 ff 48 setlo 0xff48,gr0 - 634: 80 f8 ff ff sethi 0xffff,gr0 - 638: 80 f4 00 1c setlo 0x1c,gr0 - 63c: 80 f8 00 00 sethi hi\(0x0\),gr0 +00000508 <GF0>: + 508: 80 40 f0 10 addi gr15,16,gr0 + 50c: 80 fc 00 24 setlos 0x24,gr0 + 510: 80 f4 00 20 setlo 0x20,gr0 + 514: 80 f8 00 00 sethi hi\(0x0\),gr0 + 518: 80 40 f0 0c addi gr15,12,gr0 + 51c: 80 fc 00 18 setlos 0x18,gr0 + 520: 80 f4 00 14 setlo 0x14,gr0 + 524: 80 f8 00 00 sethi hi\(0x0\),gr0 + 528: 80 40 ff f0 addi gr15,-16,gr0 + 52c: 80 fc ff e8 setlos 0xffffffe8,gr0 + 530: 80 f4 ff e0 setlo 0xffe0,gr0 + 534: 80 f8 ff ff sethi 0xffff,gr0 + 538: 80 40 ff d8 addi gr15,-40,gr0 + 53c: 80 fc ff d8 setlos 0xffffffd8,gr0 + 540: 80 f4 ff d8 setlo 0xffd8,gr0 + 544: 80 f8 ff ff sethi 0xffff,gr0 + 548: 80 f4 00 1c setlo 0x1c,gr0 + 54c: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004644 <D2>: - 4644: 00 00 00 00 add\.p gr0,gr0,gr0 - 4644: R_FRV_32 GD0 +000045e4 <D2>: + 45e4: 00 00 00 00 add\.p gr0,gr0,gr0 + 45e4: R_FRV_32 GD0 -00004648 <GD0>: +000045e8 <GD0>: \.\.\. - 4648: R_FRV_FUNCDESC GFb - 464c: R_FRV_32 GFb + 45e8: R_FRV_FUNCDESC GFb + 45ec: R_FRV_32 GFb Disassembly of section \.got: -000046e0 <_GLOBAL_OFFSET_TABLE_-0x20>: - 46e0: 00 00 05 dc subxcc\.p gr0,gr28,gr0,icc1 - 46e0: R_FRV_FUNCDESC_VALUE GF9 - 46e4: 00 00 00 00 add\.p gr0,gr0,gr0 - 46e8: 00 00 05 d4 subxcc\.p gr0,gr20,gr0,icc1 - 46e8: R_FRV_FUNCDESC_VALUE GF8 - 46ec: 00 00 00 00 add\.p gr0,gr0,gr0 - 46f0: 00 00 05 e4 subxcc\.p gr0,gr36,gr0,icc1 - 46f0: R_FRV_FUNCDESC_VALUE GF7 - 46f4: 00 00 00 00 add\.p gr0,gr0,gr0 - 46f8: 00 00 05 cc subxcc\.p gr0,gr12,gr0,icc1 - 46f8: R_FRV_FUNCDESC_VALUE GF0 - 46fc: 00 00 00 00 add\.p gr0,gr0,gr0 +000045f0 <_GLOBAL_OFFSET_TABLE_-0x20>: + 45f0: 00 00 04 ec addxcc\.p gr0,gr44,gr0,icc1 + 45f0: R_FRV_FUNCDESC_VALUE GF9 + 45f4: 00 00 00 00 add\.p gr0,gr0,gr0 + 45f8: 00 00 04 e4 addxcc\.p gr0,gr36,gr0,icc1 + 45f8: R_FRV_FUNCDESC_VALUE GF8 + 45fc: 00 00 00 00 add\.p gr0,gr0,gr0 + 4600: 00 00 04 f4 addxcc\.p gr0,gr52,gr0,icc1 + 4600: R_FRV_FUNCDESC_VALUE GF7 + 4604: 00 00 00 00 add\.p gr0,gr0,gr0 + 4608: 00 00 04 dc addxcc\.p gr0,gr28,gr0,icc1 + 4608: R_FRV_FUNCDESC_VALUE GF0 + 460c: 00 00 00 00 add\.p gr0,gr0,gr0 -00004700 <_GLOBAL_OFFSET_TABLE_>: +00004610 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 470c: R_FRV_FUNCDESC GF4 - 4710: R_FRV_32 GF1 - 4714: R_FRV_FUNCDESC GF6 - 4718: R_FRV_FUNCDESC GF5 - 471c: R_FRV_32 GD4 - 4720: R_FRV_32 GF3 - 4724: R_FRV_32 GF2 + 461c: R_FRV_FUNCDESC GF4 + 4620: R_FRV_32 GF1 + 4624: R_FRV_FUNCDESC GF6 + 4628: R_FRV_FUNCDESC GF5 + 462c: R_FRV_32 GD4 + 4630: R_FRV_32 GF3 + 4634: R_FRV_32 GF2 diff --git a/ld/testsuite/ld-frv/fdpic-shared-3.d b/ld/testsuite/ld-frv/fdpic-shared-3.d index 3c7d03a..638be7b 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-3.d +++ b/ld/testsuite/ld-frv/fdpic-shared-3.d @@ -8,77 +8,77 @@ Disassembly of section \.text: -0000042c <F3>: - 42c: 80 3c 00 01 call 430 <HF0> +0000038c <F3>: + 38c: 80 3c 00 01 call 390 <HF0> -00000430 <HF0>: - 430: 80 40 f0 0c addi gr15,12,gr0 - 434: 80 fc 00 18 setlos 0x18,gr0 - 438: 80 f4 00 1c setlo 0x1c,gr0 - 43c: 80 f8 00 00 sethi hi\(0x0\),gr0 - 440: 80 40 f0 10 addi gr15,16,gr0 - 444: 80 fc 00 20 setlos 0x20,gr0 - 448: 80 f4 00 14 setlo 0x14,gr0 - 44c: 80 f8 00 00 sethi hi\(0x0\),gr0 - 450: 80 40 ff f8 addi gr15,-8,gr0 - 454: 80 fc ff e8 setlos 0xffffffe8,gr0 - 458: 80 f4 ff d8 setlo 0xffd8,gr0 - 45c: 80 f8 ff ff sethi 0xffff,gr0 - 460: 80 40 ff 48 addi gr15,-184,gr0 - 464: 80 fc ff 48 setlos 0xffffff48,gr0 - 468: 80 f4 ff 48 setlo 0xff48,gr0 - 46c: 80 f8 ff ff sethi 0xffff,gr0 - 470: 80 f4 00 24 setlo 0x24,gr0 - 474: 80 f8 00 00 sethi hi\(0x0\),gr0 +00000390 <HF0>: + 390: 80 40 f0 0c addi gr15,12,gr0 + 394: 80 fc 00 18 setlos 0x18,gr0 + 398: 80 f4 00 1c setlo 0x1c,gr0 + 39c: 80 f8 00 00 sethi hi\(0x0\),gr0 + 3a0: 80 40 f0 10 addi gr15,16,gr0 + 3a4: 80 fc 00 20 setlos 0x20,gr0 + 3a8: 80 f4 00 14 setlo 0x14,gr0 + 3ac: 80 f8 00 00 sethi hi\(0x0\),gr0 + 3b0: 80 40 ff f8 addi gr15,-8,gr0 + 3b4: 80 fc ff e8 setlos 0xffffffe8,gr0 + 3b8: 80 f4 ff d8 setlo 0xffd8,gr0 + 3bc: 80 f8 ff ff sethi 0xffff,gr0 + 3c0: 80 40 ff c0 addi gr15,-64,gr0 + 3c4: 80 fc ff c0 setlos 0xffffffc0,gr0 + 3c8: 80 f4 ff c0 setlo 0xffc0,gr0 + 3cc: 80 f8 ff ff sethi 0xffff,gr0 + 3d0: 80 f4 00 24 setlo 0x24,gr0 + 3d4: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -0000447c <D3>: - 447c: 00 00 00 04 add\.p gr0,gr4,gr0 - 447c: R_FRV_32 \.data +00004454 <D3>: + 4454: 00 00 00 04 add\.p gr0,gr4,gr0 + 4454: R_FRV_32 \.data -00004480 <HD0>: - 4480: 00 00 00 08 add\.p gr0,gr8,gr0 - 4480: R_FRV_32 \.got - 4484: 00 00 00 04 add\.p gr0,gr4,gr0 - 4484: R_FRV_32 \.text +00004458 <HD0>: + 4458: 00 00 00 08 add\.p gr0,gr8,gr0 + 4458: R_FRV_32 \.got + 445c: 00 00 00 04 add\.p gr0,gr4,gr0 + 445c: R_FRV_32 \.text Disassembly of section \.got: -00004500 <_GLOBAL_OFFSET_TABLE_-0x38>: - 4500: 00 00 00 04 add\.p gr0,gr4,gr0 - 4500: R_FRV_FUNCDESC_VALUE \.text - 4504: 00 00 00 00 add\.p gr0,gr0,gr0 - 4508: 00 00 00 04 add\.p gr0,gr4,gr0 - 4508: R_FRV_FUNCDESC_VALUE \.text - 450c: 00 00 00 00 add\.p gr0,gr0,gr0 - 4510: 00 00 00 04 add\.p gr0,gr4,gr0 - 4510: R_FRV_FUNCDESC_VALUE \.text - 4514: 00 00 00 00 add\.p gr0,gr0,gr0 - 4518: 00 00 00 04 add\.p gr0,gr4,gr0 - 4518: R_FRV_FUNCDESC_VALUE \.text - 451c: 00 00 00 00 add\.p gr0,gr0,gr0 - 4520: 00 00 00 04 add\.p gr0,gr4,gr0 - 4520: R_FRV_FUNCDESC_VALUE \.text - 4524: 00 00 00 00 add\.p gr0,gr0,gr0 - 4528: 00 00 00 04 add\.p gr0,gr4,gr0 - 4528: R_FRV_FUNCDESC_VALUE \.text - 452c: 00 00 00 00 add\.p gr0,gr0,gr0 - 4530: 00 00 00 04 add\.p gr0,gr4,gr0 - 4530: R_FRV_FUNCDESC_VALUE \.text - 4534: 00 00 00 00 add\.p gr0,gr0,gr0 +00004460 <_GLOBAL_OFFSET_TABLE_-0x38>: + 4460: 00 00 00 04 add\.p gr0,gr4,gr0 + 4460: R_FRV_FUNCDESC_VALUE \.text + 4464: 00 00 00 00 add\.p gr0,gr0,gr0 + 4468: 00 00 00 04 add\.p gr0,gr4,gr0 + 4468: R_FRV_FUNCDESC_VALUE \.text + 446c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4470: 00 00 00 04 add\.p gr0,gr4,gr0 + 4470: R_FRV_FUNCDESC_VALUE \.text + 4474: 00 00 00 00 add\.p gr0,gr0,gr0 + 4478: 00 00 00 04 add\.p gr0,gr4,gr0 + 4478: R_FRV_FUNCDESC_VALUE \.text + 447c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4480: 00 00 00 04 add\.p gr0,gr4,gr0 + 4480: R_FRV_FUNCDESC_VALUE \.text + 4484: 00 00 00 00 add\.p gr0,gr0,gr0 + 4488: 00 00 00 04 add\.p gr0,gr4,gr0 + 4488: R_FRV_FUNCDESC_VALUE \.text + 448c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4490: 00 00 00 04 add\.p gr0,gr4,gr0 + 4490: R_FRV_FUNCDESC_VALUE \.text + 4494: 00 00 00 00 add\.p gr0,gr0,gr0 -00004538 <_GLOBAL_OFFSET_TABLE_>: +00004498 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 4544: 00 00 00 04 add\.p gr0,gr4,gr0 - 4544: R_FRV_32 \.text - 4548: 00 00 00 00 add\.p gr0,gr0,gr0 - 4548: R_FRV_32 \.got - 454c: 00 00 00 28 add\.p gr0,gr40,gr0 - 454c: R_FRV_32 \.got - 4550: 00 00 00 04 add\.p gr0,gr4,gr0 - 4550: R_FRV_32 \.text - 4554: 00 00 00 04 add\.p gr0,gr4,gr0 - 4554: R_FRV_32 \.text - 4558: 00 00 00 18 add\.p gr0,gr24,gr0 - 4558: R_FRV_32 \.got - 455c: 00 00 00 04 add\.p gr0,gr4,gr0 - 455c: R_FRV_32 \.data + 44a4: 00 00 00 04 add\.p gr0,gr4,gr0 + 44a4: R_FRV_32 \.text + 44a8: 00 00 00 00 add\.p gr0,gr0,gr0 + 44a8: R_FRV_32 \.got + 44ac: 00 00 00 28 add\.p gr0,gr40,gr0 + 44ac: R_FRV_32 \.got + 44b0: 00 00 00 04 add\.p gr0,gr4,gr0 + 44b0: R_FRV_32 \.text + 44b4: 00 00 00 04 add\.p gr0,gr4,gr0 + 44b4: R_FRV_32 \.text + 44b8: 00 00 00 18 add\.p gr0,gr24,gr0 + 44b8: R_FRV_32 \.got + 44bc: 00 00 00 04 add\.p gr0,gr4,gr0 + 44bc: R_FRV_32 \.data diff --git a/ld/testsuite/ld-frv/fdpic-shared-4.d b/ld/testsuite/ld-frv/fdpic-shared-4.d index 8c1098f..5769e86 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-4.d +++ b/ld/testsuite/ld-frv/fdpic-shared-4.d @@ -8,65 +8,65 @@ Disassembly of section \.text: -00000604 <F4>: - 604: 80 3c 00 01 call 608 <PF0> +00000564 <F4>: + 564: 80 3c 00 01 call 568 <PF0> -00000608 <PF0>: - 608: 80 40 f0 10 addi gr15,16,gr0 - 60c: 80 fc 00 20 setlos 0x20,gr0 - 610: 80 f4 00 1c setlo 0x1c,gr0 - 614: 80 f8 00 00 sethi hi\(0x0\),gr0 - 618: 80 40 f0 0c addi gr15,12,gr0 - 61c: 80 fc 00 24 setlos 0x24,gr0 - 620: 80 f4 00 18 setlo 0x18,gr0 - 624: 80 f8 00 00 sethi hi\(0x0\),gr0 - 628: 80 40 ff f8 addi gr15,-8,gr0 - 62c: 80 fc ff f0 setlos 0xfffffff0,gr0 - 630: 80 f4 ff e8 setlo 0xffe8,gr0 - 634: 80 f8 ff ff sethi 0xffff,gr0 - 638: 80 40 ff 68 addi gr15,-152,gr0 - 63c: 80 fc ff 68 setlos 0xffffff68,gr0 - 640: 80 f4 ff 68 setlo 0xff68,gr0 - 644: 80 f8 ff ff sethi 0xffff,gr0 - 648: 80 f4 00 14 setlo 0x14,gr0 - 64c: 80 f8 00 00 sethi hi\(0x0\),gr0 +00000568 <PF0>: + 568: 80 40 f0 10 addi gr15,16,gr0 + 56c: 80 fc 00 20 setlos 0x20,gr0 + 570: 80 f4 00 1c setlo 0x1c,gr0 + 574: 80 f8 00 00 sethi hi\(0x0\),gr0 + 578: 80 40 f0 0c addi gr15,12,gr0 + 57c: 80 fc 00 24 setlos 0x24,gr0 + 580: 80 f4 00 18 setlo 0x18,gr0 + 584: 80 f8 00 00 sethi hi\(0x0\),gr0 + 588: 80 40 ff f8 addi gr15,-8,gr0 + 58c: 80 fc ff f0 setlos 0xfffffff0,gr0 + 590: 80 f4 ff e8 setlo 0xffe8,gr0 + 594: 80 f8 ff ff sethi 0xffff,gr0 + 598: 80 40 ff e0 addi gr15,-32,gr0 + 59c: 80 fc ff e0 setlos 0xffffffe0,gr0 + 5a0: 80 f4 ff e0 setlo 0xffe0,gr0 + 5a4: 80 f8 ff ff sethi 0xffff,gr0 + 5a8: 80 f4 00 14 setlo 0x14,gr0 + 5ac: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004654 <D4>: - 4654: 00 00 00 04 add\.p gr0,gr4,gr0 - 4654: R_FRV_32 \.data +0000462c <D4>: + 462c: 00 00 00 04 add\.p gr0,gr4,gr0 + 462c: R_FRV_32 \.data -00004658 <PD0>: - 4658: 00 00 00 04 add\.p gr0,gr4,gr0 - 4658: R_FRV_FUNCDESC \.text - 465c: 00 00 00 04 add\.p gr0,gr4,gr0 - 465c: R_FRV_32 \.text +00004630 <PD0>: + 4630: 00 00 00 04 add\.p gr0,gr4,gr0 + 4630: R_FRV_FUNCDESC \.text + 4634: 00 00 00 04 add\.p gr0,gr4,gr0 + 4634: R_FRV_32 \.text Disassembly of section \.got: -000046d8 <_GLOBAL_OFFSET_TABLE_-0x18>: - 46d8: 00 00 00 04 add\.p gr0,gr4,gr0 - 46d8: R_FRV_FUNCDESC_VALUE \.text - 46dc: 00 00 00 00 add\.p gr0,gr0,gr0 - 46e0: 00 00 00 04 add\.p gr0,gr4,gr0 - 46e0: R_FRV_FUNCDESC_VALUE \.text - 46e4: 00 00 00 00 add\.p gr0,gr0,gr0 - 46e8: 00 00 00 04 add\.p gr0,gr4,gr0 - 46e8: R_FRV_FUNCDESC_VALUE \.text - 46ec: 00 00 00 00 add\.p gr0,gr0,gr0 +00004638 <_GLOBAL_OFFSET_TABLE_-0x18>: + 4638: 00 00 00 04 add\.p gr0,gr4,gr0 + 4638: R_FRV_FUNCDESC_VALUE \.text + 463c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4640: 00 00 00 04 add\.p gr0,gr4,gr0 + 4640: R_FRV_FUNCDESC_VALUE \.text + 4644: 00 00 00 00 add\.p gr0,gr0,gr0 + 4648: 00 00 00 04 add\.p gr0,gr4,gr0 + 4648: R_FRV_FUNCDESC_VALUE \.text + 464c: 00 00 00 00 add\.p gr0,gr0,gr0 -000046f0 <_GLOBAL_OFFSET_TABLE_>: +00004650 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 46fc: 00 00 00 04 add\.p gr0,gr4,gr0 - 46fc: R_FRV_FUNCDESC \.text - 4700: 00 00 00 04 add\.p gr0,gr4,gr0 - 4700: R_FRV_32 \.text - 4704: 00 00 00 04 add\.p gr0,gr4,gr0 - 4704: R_FRV_32 \.data - 4708: 00 00 00 04 add\.p gr0,gr4,gr0 - 4708: R_FRV_FUNCDESC \.text - 470c: 00 00 00 04 add\.p gr0,gr4,gr0 - 470c: R_FRV_32 \.text - 4710: 00 00 00 04 add\.p gr0,gr4,gr0 - 4710: R_FRV_32 \.text - 4714: 00 00 00 04 add\.p gr0,gr4,gr0 - 4714: R_FRV_FUNCDESC \.text + 465c: 00 00 00 04 add\.p gr0,gr4,gr0 + 465c: R_FRV_FUNCDESC \.text + 4660: 00 00 00 04 add\.p gr0,gr4,gr0 + 4660: R_FRV_32 \.text + 4664: 00 00 00 04 add\.p gr0,gr4,gr0 + 4664: R_FRV_32 \.data + 4668: 00 00 00 04 add\.p gr0,gr4,gr0 + 4668: R_FRV_FUNCDESC \.text + 466c: 00 00 00 04 add\.p gr0,gr4,gr0 + 466c: R_FRV_32 \.text + 4670: 00 00 00 04 add\.p gr0,gr4,gr0 + 4670: R_FRV_32 \.text + 4674: 00 00 00 04 add\.p gr0,gr4,gr0 + 4674: R_FRV_FUNCDESC \.text diff --git a/ld/testsuite/ld-frv/fdpic-shared-5.d b/ld/testsuite/ld-frv/fdpic-shared-5.d index 9fcc933..f7f9d31 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-5.d +++ b/ld/testsuite/ld-frv/fdpic-shared-5.d @@ -8,76 +8,76 @@ Disassembly of section \.plt: -00000598 <\.plt>: - 598: 00 00 00 10 add\.p gr0,gr16,gr0 - 59c: c0 1a 00 06 bra 5b4 <F5-0x10> - 5a0: 00 00 00 08 add\.p gr0,gr8,gr0 - 5a4: c0 1a 00 04 bra 5b4 <F5-0x10> - 5a8: 00 00 00 00 add\.p gr0,gr0,gr0 - 5ac: c0 1a 00 02 bra 5b4 <F5-0x10> - 5b0: 00 00 00 18 add\.p gr0,gr24,gr0 - 5b4: 88 08 f1 40 ldd @\(gr15,gr0\),gr4 - 5b8: 80 30 40 00 jmpl @\(gr4,gr0\) - 5bc: 9c cc ff f0 lddi @\(gr15,-16\),gr14 - 5c0: 80 30 e0 00 jmpl @\(gr14,gr0\) +000004a8 <\.plt>: + 4a8: 00 00 00 10 add\.p gr0,gr16,gr0 + 4ac: c0 1a 00 06 bra 4c4 <F5-0x10> + 4b0: 00 00 00 08 add\.p gr0,gr8,gr0 + 4b4: c0 1a 00 04 bra 4c4 <F5-0x10> + 4b8: 00 00 00 00 add\.p gr0,gr0,gr0 + 4bc: c0 1a 00 02 bra 4c4 <F5-0x10> + 4c0: 00 00 00 18 add\.p gr0,gr24,gr0 + 4c4: 88 08 f1 40 ldd @\(gr15,gr0\),gr4 + 4c8: 80 30 40 00 jmpl @\(gr4,gr0\) + 4cc: 9c cc ff f0 lddi @\(gr15,-16\),gr14 + 4d0: 80 30 e0 00 jmpl @\(gr14,gr0\) Disassembly of section \.text: -000005c4 <F5>: - 5c4: fe 3f ff fe call 5bc <F5-0x8> - 5c8: 80 40 f0 0c addi gr15,12,gr0 - 5cc: 80 fc 00 24 setlos 0x24,gr0 - 5d0: 80 f4 00 20 setlo 0x20,gr0 - 5d4: 80 f8 00 00 sethi hi\(0x0\),gr0 - 5d8: 80 40 f0 10 addi gr15,16,gr0 - 5dc: 80 fc 00 1c setlos 0x1c,gr0 - 5e0: 80 f4 00 18 setlo 0x18,gr0 - 5e4: 80 f8 00 00 sethi hi\(0x0\),gr0 - 5e8: 80 40 ff f8 addi gr15,-8,gr0 - 5ec: 80 fc ff e8 setlos 0xffffffe8,gr0 - 5f0: 80 f4 ff e0 setlo 0xffe0,gr0 - 5f4: 80 f8 ff ff sethi 0xffff,gr0 - 5f8: 80 f4 00 14 setlo 0x14,gr0 - 5fc: 80 f8 00 00 sethi hi\(0x0\),gr0 +000004d4 <F5>: + 4d4: fe 3f ff fe call 4cc <F5-0x8> + 4d8: 80 40 f0 0c addi gr15,12,gr0 + 4dc: 80 fc 00 24 setlos 0x24,gr0 + 4e0: 80 f4 00 20 setlo 0x20,gr0 + 4e4: 80 f8 00 00 sethi hi\(0x0\),gr0 + 4e8: 80 40 f0 10 addi gr15,16,gr0 + 4ec: 80 fc 00 1c setlos 0x1c,gr0 + 4f0: 80 f4 00 18 setlo 0x18,gr0 + 4f4: 80 f8 00 00 sethi hi\(0x0\),gr0 + 4f8: 80 40 ff f8 addi gr15,-8,gr0 + 4fc: 80 fc ff e8 setlos 0xffffffe8,gr0 + 500: 80 f4 ff e0 setlo 0xffe0,gr0 + 504: 80 f8 ff ff sethi 0xffff,gr0 + 508: 80 f4 00 14 setlo 0x14,gr0 + 50c: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004604 <D5>: - 4604: 00 00 00 00 add\.p gr0,gr0,gr0 - 4604: R_FRV_32 UD0 - 4608: 00 00 00 00 add\.p gr0,gr0,gr0 - 4608: R_FRV_FUNCDESC UFb - 460c: 00 00 00 00 add\.p gr0,gr0,gr0 - 460c: R_FRV_32 UFb +000045a4 <D5>: + 45a4: 00 00 00 00 add\.p gr0,gr0,gr0 + 45a4: R_FRV_32 UD0 + 45a8: 00 00 00 00 add\.p gr0,gr0,gr0 + 45a8: R_FRV_FUNCDESC UFb + 45ac: 00 00 00 00 add\.p gr0,gr0,gr0 + 45ac: R_FRV_32 UFb Disassembly of section \.got: -000046a0 <_GLOBAL_OFFSET_TABLE_-0x20>: - 46a0: 00 00 05 b4 subx\.p gr0,gr52,gr0,icc1 - 46a0: R_FRV_FUNCDESC_VALUE UF9 - 46a4: 00 00 00 00 add\.p gr0,gr0,gr0 - 46a8: 00 00 05 9c subx\.p gr0,gr28,gr0,icc1 - 46a8: R_FRV_FUNCDESC_VALUE UF8 - 46ac: 00 00 00 00 add\.p gr0,gr0,gr0 - 46b0: 00 00 05 ac subx\.p gr0,gr44,gr0,icc1 - 46b0: R_FRV_FUNCDESC_VALUE UF0 - 46b4: 00 00 00 00 add\.p gr0,gr0,gr0 - 46b8: 00 00 05 a4 subx\.p gr0,gr36,gr0,icc1 - 46b8: R_FRV_FUNCDESC_VALUE UF7 - 46bc: 00 00 00 00 add\.p gr0,gr0,gr0 +000045b0 <_GLOBAL_OFFSET_TABLE_-0x20>: + 45b0: 00 00 04 c4 addxcc\.p gr0,gr4,gr0,icc1 + 45b0: R_FRV_FUNCDESC_VALUE UF9 + 45b4: 00 00 00 00 add\.p gr0,gr0,gr0 + 45b8: 00 00 04 ac addx\.p gr0,gr44,gr0,icc1 + 45b8: R_FRV_FUNCDESC_VALUE UF8 + 45bc: 00 00 00 00 add\.p gr0,gr0,gr0 + 45c0: 00 00 04 bc addx\.p gr0,gr60,gr0,icc1 + 45c0: R_FRV_FUNCDESC_VALUE UF0 + 45c4: 00 00 00 00 add\.p gr0,gr0,gr0 + 45c8: 00 00 04 b4 addx\.p gr0,gr52,gr0,icc1 + 45c8: R_FRV_FUNCDESC_VALUE UF7 + 45cc: 00 00 00 00 add\.p gr0,gr0,gr0 -000046c0 <_GLOBAL_OFFSET_TABLE_>: - 46c0: 00 00 00 00 add\.p gr0,gr0,gr0 - 46c4: 00 00 00 00 add\.p gr0,gr0,gr0 - 46c8: 00 00 00 00 add\.p gr0,gr0,gr0 - 46cc: 00 00 00 00 add\.p gr0,gr0,gr0 - 46cc: R_FRV_32 UF1 - 46d0: 00 00 00 00 add\.p gr0,gr0,gr0 - 46d0: R_FRV_FUNCDESC UF4 - 46d4: 00 00 00 00 add\.p gr0,gr0,gr0 - 46d4: R_FRV_32 UD1 - 46d8: 00 00 00 00 add\.p gr0,gr0,gr0 - 46d8: R_FRV_FUNCDESC UF6 - 46dc: 00 00 00 00 add\.p gr0,gr0,gr0 - 46dc: R_FRV_FUNCDESC UF5 - 46e0: 00 00 00 00 add\.p gr0,gr0,gr0 - 46e0: R_FRV_32 UF3 - 46e4: 00 00 00 00 add\.p gr0,gr0,gr0 - 46e4: R_FRV_32 UF2 +000045d0 <_GLOBAL_OFFSET_TABLE_>: + 45d0: 00 00 00 00 add\.p gr0,gr0,gr0 + 45d4: 00 00 00 00 add\.p gr0,gr0,gr0 + 45d8: 00 00 00 00 add\.p gr0,gr0,gr0 + 45dc: 00 00 00 00 add\.p gr0,gr0,gr0 + 45dc: R_FRV_32 UF1 + 45e0: 00 00 00 00 add\.p gr0,gr0,gr0 + 45e0: R_FRV_FUNCDESC UF4 + 45e4: 00 00 00 00 add\.p gr0,gr0,gr0 + 45e4: R_FRV_32 UD1 + 45e8: 00 00 00 00 add\.p gr0,gr0,gr0 + 45e8: R_FRV_FUNCDESC UF6 + 45ec: 00 00 00 00 add\.p gr0,gr0,gr0 + 45ec: R_FRV_FUNCDESC UF5 + 45f0: 00 00 00 00 add\.p gr0,gr0,gr0 + 45f0: R_FRV_32 UF3 + 45f4: 00 00 00 00 add\.p gr0,gr0,gr0 + 45f4: R_FRV_32 UF2 diff --git a/ld/testsuite/ld-frv/fdpic-shared-6.d b/ld/testsuite/ld-frv/fdpic-shared-6.d index 8b5168c..0d18336 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-6.d +++ b/ld/testsuite/ld-frv/fdpic-shared-6.d @@ -8,67 +8,67 @@ Disassembly of section \.plt: -0000041c <\.plt>: - 41c: 00 00 00 08 add\.p gr0,gr8,gr0 - 420: c0 1a 00 06 bra 438 <F6-0x10> - 424: 00 00 00 00 add\.p gr0,gr0,gr0 - 428: c0 1a 00 04 bra 438 <F6-0x10> - 42c: 00 00 00 10 add\.p gr0,gr16,gr0 - 430: c0 1a 00 02 bra 438 <F6-0x10> - 434: 00 00 00 18 add\.p gr0,gr24,gr0 - 438: 88 08 f1 40 ldd @\(gr15,gr0\),gr4 - 43c: 80 30 40 00 jmpl @\(gr4,gr0\) - 440: 9c cc ff f0 lddi @\(gr15,-16\),gr14 - 444: 80 30 e0 00 jmpl @\(gr14,gr0\) +0000037c <\.plt>: + 37c: 00 00 00 08 add\.p gr0,gr8,gr0 + 380: c0 1a 00 06 bra 398 <F6-0x10> + 384: 00 00 00 00 add\.p gr0,gr0,gr0 + 388: c0 1a 00 04 bra 398 <F6-0x10> + 38c: 00 00 00 10 add\.p gr0,gr16,gr0 + 390: c0 1a 00 02 bra 398 <F6-0x10> + 394: 00 00 00 18 add\.p gr0,gr24,gr0 + 398: 88 08 f1 40 ldd @\(gr15,gr0\),gr4 + 39c: 80 30 40 00 jmpl @\(gr4,gr0\) + 3a0: 9c cc ff f0 lddi @\(gr15,-16\),gr14 + 3a4: 80 30 e0 00 jmpl @\(gr14,gr0\) Disassembly of section \.text: -00000448 <F6>: - 448: fe 3f ff fe call 440 <F6-0x8> - 44c: 80 40 f0 0c addi gr15,12,gr0 - 450: 80 fc 00 24 setlos 0x24,gr0 - 454: 80 f4 00 20 setlo 0x20,gr0 - 458: 80 f8 00 00 sethi hi\(0x0\),gr0 - 45c: 80 40 f0 10 addi gr15,16,gr0 - 460: 80 fc 00 18 setlos 0x18,gr0 - 464: 80 f4 00 1c setlo 0x1c,gr0 - 468: 80 f8 00 00 sethi hi\(0x0\),gr0 - 46c: 80 40 ff f8 addi gr15,-8,gr0 - 470: 80 fc ff e8 setlos 0xffffffe8,gr0 - 474: 80 f4 ff e0 setlo 0xffe0,gr0 - 478: 80 f8 ff ff sethi 0xffff,gr0 - 47c: 80 f4 ff 40 setlo 0xff40,gr0 - 480: 80 f8 ff ff sethi 0xffff,gr0 - 484: 80 f4 00 14 setlo 0x14,gr0 - 488: 80 f8 00 00 sethi hi\(0x0\),gr0 +000003a8 <F6>: + 3a8: fe 3f ff fe call 3a0 <F6-0x8> + 3ac: 80 40 f0 0c addi gr15,12,gr0 + 3b0: 80 fc 00 24 setlos 0x24,gr0 + 3b4: 80 f4 00 20 setlo 0x20,gr0 + 3b8: 80 f8 00 00 sethi hi\(0x0\),gr0 + 3bc: 80 40 f0 10 addi gr15,16,gr0 + 3c0: 80 fc 00 18 setlos 0x18,gr0 + 3c4: 80 f4 00 1c setlo 0x1c,gr0 + 3c8: 80 f8 00 00 sethi hi\(0x0\),gr0 + 3cc: 80 40 ff f8 addi gr15,-8,gr0 + 3d0: 80 fc ff e8 setlos 0xffffffe8,gr0 + 3d4: 80 f4 ff e0 setlo 0xffe0,gr0 + 3d8: 80 f8 ff ff sethi 0xffff,gr0 + 3dc: 80 f4 ff d0 setlo 0xffd0,gr0 + 3e0: 80 f8 ff ff sethi 0xffff,gr0 + 3e4: 80 f4 00 14 setlo 0x14,gr0 + 3e8: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004490 <D6>: +00004480 <D6>: \.\.\. - 4490: R_FRV_32 WD0 - 4494: R_FRV_FUNCDESC WFb - 4498: R_FRV_32 WFb + 4480: R_FRV_32 WD0 + 4484: R_FRV_FUNCDESC WFb + 4488: R_FRV_32 WFb Disassembly of section \.got: -00004530 <_GLOBAL_OFFSET_TABLE_-0x20>: - 4530: 00 00 04 38 \*unknown\* - 4530: R_FRV_FUNCDESC_VALUE WF9 - 4534: 00 00 00 00 add\.p gr0,gr0,gr0 - 4538: 00 00 04 30 \*unknown\* - 4538: R_FRV_FUNCDESC_VALUE WF8 - 453c: 00 00 00 00 add\.p gr0,gr0,gr0 - 4540: 00 00 04 28 \*unknown\* - 4540: R_FRV_FUNCDESC_VALUE WF0 - 4544: 00 00 00 00 add\.p gr0,gr0,gr0 - 4548: 00 00 04 20 \*unknown\* - 4548: R_FRV_FUNCDESC_VALUE WF7 - 454c: 00 00 00 00 add\.p gr0,gr0,gr0 +00004490 <_GLOBAL_OFFSET_TABLE_-0x20>: + 4490: 00 00 03 98 sdiv\.p gr0,gr24,gr0 + 4490: R_FRV_FUNCDESC_VALUE WF9 + 4494: 00 00 00 00 add\.p gr0,gr0,gr0 + 4498: 00 00 03 90 sdiv\.p gr0,gr16,gr0 + 4498: R_FRV_FUNCDESC_VALUE WF8 + 449c: 00 00 00 00 add\.p gr0,gr0,gr0 + 44a0: 00 00 03 88 sdiv\.p gr0,gr8,gr0 + 44a0: R_FRV_FUNCDESC_VALUE WF0 + 44a4: 00 00 00 00 add\.p gr0,gr0,gr0 + 44a8: 00 00 03 80 sdiv\.p gr0,gr0,gr0 + 44a8: R_FRV_FUNCDESC_VALUE WF7 + 44ac: 00 00 00 00 add\.p gr0,gr0,gr0 -00004550 <_GLOBAL_OFFSET_TABLE_>: +000044b0 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 455c: R_FRV_32 WF1 - 4560: R_FRV_FUNCDESC WF4 - 4564: R_FRV_32 WD2 - 4568: R_FRV_FUNCDESC WF5 - 456c: R_FRV_FUNCDESC WF6 - 4570: R_FRV_32 WF3 - 4574: R_FRV_32 WF2 + 44bc: R_FRV_32 WF1 + 44c0: R_FRV_FUNCDESC WF4 + 44c4: R_FRV_32 WD2 + 44c8: R_FRV_FUNCDESC WF5 + 44cc: R_FRV_FUNCDESC WF6 + 44d0: R_FRV_32 WF3 + 44d4: R_FRV_32 WF2 diff --git a/ld/testsuite/ld-frv/fdpic-shared-7.d b/ld/testsuite/ld-frv/fdpic-shared-7.d index 80c26d3..0a1464f 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-7.d +++ b/ld/testsuite/ld-frv/fdpic-shared-7.d @@ -8,51 +8,51 @@ Disassembly of section \.text: -000003dc <F7>: - 3dc: 80 3c 00 02 call 3e4 <\.F0\+0x4> - -000003e0 <\.F0>: - 3e0: 80 40 f0 0c addi gr15,12,gr0 - 3e4: 80 fc 00 0c setlos 0xc,gr0 - 3e8: 80 f4 00 0c setlo 0xc,gr0 - 3ec: 80 f8 00 00 sethi hi\(0x0\),gr0 - 3f0: 80 40 f0 10 addi gr15,16,gr0 - 3f4: 80 fc 00 10 setlos 0x10,gr0 - 3f8: 80 f4 00 10 setlo 0x10,gr0 - 3fc: 80 f8 00 00 sethi hi\(0x0\),gr0 - 400: 80 40 ff f8 addi gr15,-8,gr0 - 404: 80 fc ff f8 setlos 0xfffffff8,gr0 - 408: 80 f4 ff f8 setlo 0xfff8,gr0 - 40c: 80 f8 ff ff sethi 0xffff,gr0 - 410: 80 40 ff 7c addi gr15,-132,gr0 - 414: 80 fc ff 7c setlos 0xffffff7c,gr0 - 418: 80 f4 ff 7c setlo 0xff7c,gr0 - 41c: 80 f8 ff ff sethi 0xffff,gr0 - 420: 80 f4 00 14 setlo 0x14,gr0 - 424: 80 f8 00 00 sethi hi\(0x0\),gr0 +0000033c <F7>: + 33c: 80 3c 00 02 call 344 <\.F0\+0x4> + +00000340 <\.F0>: + 340: 80 40 f0 0c addi gr15,12,gr0 + 344: 80 fc 00 0c setlos 0xc,gr0 + 348: 80 f4 00 0c setlo 0xc,gr0 + 34c: 80 f8 00 00 sethi hi\(0x0\),gr0 + 350: 80 40 f0 10 addi gr15,16,gr0 + 354: 80 fc 00 10 setlos 0x10,gr0 + 358: 80 f4 00 10 setlo 0x10,gr0 + 35c: 80 f8 00 00 sethi hi\(0x0\),gr0 + 360: 80 40 ff f8 addi gr15,-8,gr0 + 364: 80 fc ff f8 setlos 0xfffffff8,gr0 + 368: 80 f4 ff f8 setlo 0xfff8,gr0 + 36c: 80 f8 ff ff sethi 0xffff,gr0 + 370: 80 40 ff f4 addi gr15,-12,gr0 + 374: 80 fc ff f4 setlos 0xfffffff4,gr0 + 378: 80 f4 ff f4 setlo 0xfff4,gr0 + 37c: 80 f8 ff ff sethi 0xffff,gr0 + 380: 80 f4 00 14 setlo 0x14,gr0 + 384: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -0000442c <D7>: - 442c: 00 00 00 08 add\.p gr0,gr8,gr0 - 442c: R_FRV_32 \.data +00004404 <D7>: + 4404: 00 00 00 08 add\.p gr0,gr8,gr0 + 4404: R_FRV_32 \.data -00004430 <\.D0>: - 4430: 00 00 00 00 add\.p gr0,gr0,gr0 - 4430: R_FRV_32 \.got - 4434: 00 00 00 08 add\.p gr0,gr8,gr0 - 4434: R_FRV_32 \.text +00004408 <\.D0>: + 4408: 00 00 00 00 add\.p gr0,gr0,gr0 + 4408: R_FRV_32 \.got + 440c: 00 00 00 08 add\.p gr0,gr8,gr0 + 440c: R_FRV_32 \.text Disassembly of section \.got: -000044b0 <_GLOBAL_OFFSET_TABLE_-0x8>: - 44b0: 00 00 00 08 add\.p gr0,gr8,gr0 - 44b0: R_FRV_FUNCDESC_VALUE \.text - 44b4: 00 00 00 00 add\.p gr0,gr0,gr0 +00004410 <_GLOBAL_OFFSET_TABLE_-0x8>: + 4410: 00 00 00 08 add\.p gr0,gr8,gr0 + 4410: R_FRV_FUNCDESC_VALUE \.text + 4414: 00 00 00 00 add\.p gr0,gr0,gr0 -000044b8 <_GLOBAL_OFFSET_TABLE_>: +00004418 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 44c4: 00 00 00 08 add\.p gr0,gr8,gr0 - 44c4: R_FRV_32 \.text - 44c8: 00 00 00 00 add\.p gr0,gr0,gr0 - 44c8: R_FRV_32 \.got - 44cc: 00 00 00 08 add\.p gr0,gr8,gr0 - 44cc: R_FRV_32 \.data + 4424: 00 00 00 08 add\.p gr0,gr8,gr0 + 4424: R_FRV_32 \.text + 4428: 00 00 00 00 add\.p gr0,gr0,gr0 + 4428: R_FRV_32 \.got + 442c: 00 00 00 08 add\.p gr0,gr8,gr0 + 442c: R_FRV_32 \.data diff --git a/ld/testsuite/ld-frv/fdpic-shared-8.d b/ld/testsuite/ld-frv/fdpic-shared-8.d index 26a5925..a546165 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-8.d +++ b/ld/testsuite/ld-frv/fdpic-shared-8.d @@ -8,77 +8,77 @@ Disassembly of section \.text: -000004d4 <F8>: - 4d4: 80 3c 00 02 call 4dc <GF1\+0x4> +00000434 <F8>: + 434: 80 3c 00 02 call 43c <GF1\+0x4> -000004d8 <GF1>: - 4d8: 80 40 f0 10 addi gr15,16,gr0 - 4dc: 80 fc 00 14 setlos 0x14,gr0 - 4e0: 80 f4 00 24 setlo 0x24,gr0 - 4e4: 80 f8 00 00 sethi hi\(0x0\),gr0 - 4e8: 80 40 f0 0c addi gr15,12,gr0 - 4ec: 80 fc 00 1c setlos 0x1c,gr0 - 4f0: 80 f4 00 18 setlo 0x18,gr0 - 4f4: 80 f8 00 00 sethi hi\(0x0\),gr0 - 4f8: 80 40 ff f8 addi gr15,-8,gr0 - 4fc: 80 fc ff f0 setlos 0xfffffff0,gr0 - 500: 80 f4 ff c8 setlo 0xffc8,gr0 - 504: 80 f8 ff ff sethi 0xffff,gr0 - 508: 80 40 ff 4c addi gr15,-180,gr0 - 50c: 80 fc ff 4c setlos 0xffffff4c,gr0 - 510: 80 f4 ff 4c setlo 0xff4c,gr0 - 514: 80 f8 ff ff sethi 0xffff,gr0 - 518: 80 f4 00 20 setlo 0x20,gr0 - 51c: 80 f8 00 00 sethi hi\(0x0\),gr0 +00000438 <GF1>: + 438: 80 40 f0 10 addi gr15,16,gr0 + 43c: 80 fc 00 14 setlos 0x14,gr0 + 440: 80 f4 00 24 setlo 0x24,gr0 + 444: 80 f8 00 00 sethi hi\(0x0\),gr0 + 448: 80 40 f0 0c addi gr15,12,gr0 + 44c: 80 fc 00 1c setlos 0x1c,gr0 + 450: 80 f4 00 18 setlo 0x18,gr0 + 454: 80 f8 00 00 sethi hi\(0x0\),gr0 + 458: 80 40 ff f8 addi gr15,-8,gr0 + 45c: 80 fc ff f0 setlos 0xfffffff0,gr0 + 460: 80 f4 ff c8 setlo 0xffc8,gr0 + 464: 80 f8 ff ff sethi 0xffff,gr0 + 468: 80 40 ff c4 addi gr15,-60,gr0 + 46c: 80 fc ff c4 setlos 0xffffffc4,gr0 + 470: 80 f4 ff c4 setlo 0xffc4,gr0 + 474: 80 f8 ff ff sethi 0xffff,gr0 + 478: 80 f4 00 20 setlo 0x20,gr0 + 47c: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004524 <D8>: - 4524: 00 00 00 04 add\.p gr0,gr4,gr0 - 4524: R_FRV_32 GD0 +000044fc <D8>: + 44fc: 00 00 00 04 add\.p gr0,gr4,gr0 + 44fc: R_FRV_32 GD0 -00004528 <GD0>: - 4528: 00 00 00 10 add\.p gr0,gr16,gr0 - 4528: R_FRV_32 \.got - 452c: 00 00 00 08 add\.p gr0,gr8,gr0 - 452c: R_FRV_32 \.text +00004500 <GD0>: + 4500: 00 00 00 10 add\.p gr0,gr16,gr0 + 4500: R_FRV_32 \.got + 4504: 00 00 00 08 add\.p gr0,gr8,gr0 + 4504: R_FRV_32 \.text Disassembly of section \.got: -000045a8 <_GLOBAL_OFFSET_TABLE_-0x38>: - 45a8: 00 00 00 08 add\.p gr0,gr8,gr0 - 45a8: R_FRV_FUNCDESC_VALUE \.text - 45ac: 00 00 00 00 add\.p gr0,gr0,gr0 - 45b0: 00 00 00 08 add\.p gr0,gr8,gr0 - 45b0: R_FRV_FUNCDESC_VALUE \.text - 45b4: 00 00 00 00 add\.p gr0,gr0,gr0 - 45b8: 00 00 00 08 add\.p gr0,gr8,gr0 - 45b8: R_FRV_FUNCDESC_VALUE \.text - 45bc: 00 00 00 00 add\.p gr0,gr0,gr0 - 45c0: 00 00 00 08 add\.p gr0,gr8,gr0 - 45c0: R_FRV_FUNCDESC_VALUE \.text - 45c4: 00 00 00 00 add\.p gr0,gr0,gr0 - 45c8: 00 00 00 08 add\.p gr0,gr8,gr0 - 45c8: R_FRV_FUNCDESC_VALUE \.text - 45cc: 00 00 00 00 add\.p gr0,gr0,gr0 - 45d0: 00 00 00 08 add\.p gr0,gr8,gr0 - 45d0: R_FRV_FUNCDESC_VALUE \.text - 45d4: 00 00 00 00 add\.p gr0,gr0,gr0 - 45d8: 00 00 00 08 add\.p gr0,gr8,gr0 - 45d8: R_FRV_FUNCDESC_VALUE \.text - 45dc: 00 00 00 00 add\.p gr0,gr0,gr0 +00004508 <_GLOBAL_OFFSET_TABLE_-0x38>: + 4508: 00 00 00 08 add\.p gr0,gr8,gr0 + 4508: R_FRV_FUNCDESC_VALUE \.text + 450c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4510: 00 00 00 08 add\.p gr0,gr8,gr0 + 4510: R_FRV_FUNCDESC_VALUE \.text + 4514: 00 00 00 00 add\.p gr0,gr0,gr0 + 4518: 00 00 00 08 add\.p gr0,gr8,gr0 + 4518: R_FRV_FUNCDESC_VALUE \.text + 451c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4520: 00 00 00 08 add\.p gr0,gr8,gr0 + 4520: R_FRV_FUNCDESC_VALUE \.text + 4524: 00 00 00 00 add\.p gr0,gr0,gr0 + 4528: 00 00 00 08 add\.p gr0,gr8,gr0 + 4528: R_FRV_FUNCDESC_VALUE \.text + 452c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4530: 00 00 00 08 add\.p gr0,gr8,gr0 + 4530: R_FRV_FUNCDESC_VALUE \.text + 4534: 00 00 00 00 add\.p gr0,gr0,gr0 + 4538: 00 00 00 08 add\.p gr0,gr8,gr0 + 4538: R_FRV_FUNCDESC_VALUE \.text + 453c: 00 00 00 00 add\.p gr0,gr0,gr0 -000045e0 <_GLOBAL_OFFSET_TABLE_>: +00004540 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 45ec: 00 00 00 08 add\.p gr0,gr8,gr0 - 45ec: R_FRV_32 \.got - 45f0: 00 00 00 04 add\.p gr0,gr4,gr0 - 45f0: R_FRV_32 GF1 - 45f4: 00 00 00 04 add\.p gr0,gr4,gr0 - 45f4: R_FRV_32 GF2 - 45f8: 00 00 00 20 add\.p gr0,gr32,gr0 - 45f8: R_FRV_32 \.got - 45fc: 00 00 00 18 add\.p gr0,gr24,gr0 - 45fc: R_FRV_32 \.got - 4600: 00 00 00 04 add\.p gr0,gr4,gr0 - 4600: R_FRV_32 GD4 - 4604: 00 00 00 04 add\.p gr0,gr4,gr0 - 4604: R_FRV_32 GF3 + 454c: 00 00 00 08 add\.p gr0,gr8,gr0 + 454c: R_FRV_32 \.got + 4550: 00 00 00 04 add\.p gr0,gr4,gr0 + 4550: R_FRV_32 GF1 + 4554: 00 00 00 04 add\.p gr0,gr4,gr0 + 4554: R_FRV_32 GF2 + 4558: 00 00 00 20 add\.p gr0,gr32,gr0 + 4558: R_FRV_32 \.got + 455c: 00 00 00 18 add\.p gr0,gr24,gr0 + 455c: R_FRV_32 \.got + 4560: 00 00 00 04 add\.p gr0,gr4,gr0 + 4560: R_FRV_32 GD4 + 4564: 00 00 00 04 add\.p gr0,gr4,gr0 + 4564: R_FRV_32 GF3 diff --git a/ld/testsuite/ld-frv/fdpic-shared-local-2.d b/ld/testsuite/ld-frv/fdpic-shared-local-2.d index a857a2f..67fa6d1 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-local-2.d +++ b/ld/testsuite/ld-frv/fdpic-shared-local-2.d @@ -8,77 +8,77 @@ Disassembly of section \.text: -00000300 <F2>: - 300: 80 3c 00 01 call 304 <GF0> +00000228 <F2>: + 228: 80 3c 00 01 call 22c <GF0> -00000304 <GF0>: - 304: 80 40 f0 10 addi gr15,16,gr0 - 308: 80 fc 00 24 setlos 0x24,gr0 - 30c: 80 f4 00 20 setlo 0x20,gr0 - 310: 80 f8 00 00 sethi hi\(0x0\),gr0 - 314: 80 40 f0 0c addi gr15,12,gr0 - 318: 80 fc 00 18 setlos 0x18,gr0 - 31c: 80 f4 00 14 setlo 0x14,gr0 - 320: 80 f8 00 00 sethi hi\(0x0\),gr0 - 324: 80 40 ff f8 addi gr15,-8,gr0 - 328: 80 fc ff d0 setlos 0xffffffd0,gr0 - 32c: 80 f4 ff c8 setlo 0xffc8,gr0 - 330: 80 f8 ff ff sethi 0xffff,gr0 - 334: 80 40 ff 44 addi gr15,-188,gr0 - 338: 80 fc ff 44 setlos 0xffffff44,gr0 - 33c: 80 f4 ff 44 setlo 0xff44,gr0 - 340: 80 f8 ff ff sethi 0xffff,gr0 - 344: 80 f4 00 1c setlo 0x1c,gr0 - 348: 80 f8 00 00 sethi hi\(0x0\),gr0 +0000022c <GF0>: + 22c: 80 40 f0 10 addi gr15,16,gr0 + 230: 80 fc 00 24 setlos 0x24,gr0 + 234: 80 f4 00 20 setlo 0x20,gr0 + 238: 80 f8 00 00 sethi hi\(0x0\),gr0 + 23c: 80 40 f0 0c addi gr15,12,gr0 + 240: 80 fc 00 18 setlos 0x18,gr0 + 244: 80 f4 00 14 setlo 0x14,gr0 + 248: 80 f8 00 00 sethi hi\(0x0\),gr0 + 24c: 80 40 ff f8 addi gr15,-8,gr0 + 250: 80 fc ff d0 setlos 0xffffffd0,gr0 + 254: 80 f4 ff c8 setlo 0xffc8,gr0 + 258: 80 f8 ff ff sethi 0xffff,gr0 + 25c: 80 40 ff bc addi gr15,-68,gr0 + 260: 80 fc ff bc setlos 0xffffffbc,gr0 + 264: 80 f4 ff bc setlo 0xffbc,gr0 + 268: 80 f8 ff ff sethi 0xffff,gr0 + 26c: 80 f4 00 1c setlo 0x1c,gr0 + 270: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004350 <D2>: - 4350: 00 00 00 04 add\.p gr0,gr4,gr0 - 4350: R_FRV_32 \.data +000042f0 <D2>: + 42f0: 00 00 00 04 add\.p gr0,gr4,gr0 + 42f0: R_FRV_32 \.data -00004354 <GD0>: - 4354: 00 00 00 18 add\.p gr0,gr24,gr0 - 4354: R_FRV_32 \.got - 4358: 00 00 00 04 add\.p gr0,gr4,gr0 - 4358: R_FRV_32 \.text +000042f4 <GD0>: + 42f4: 00 00 00 18 add\.p gr0,gr24,gr0 + 42f4: R_FRV_32 \.got + 42f8: 00 00 00 04 add\.p gr0,gr4,gr0 + 42f8: R_FRV_32 \.text Disassembly of section \.got: -000043d8 <_GLOBAL_OFFSET_TABLE_-0x38>: - 43d8: 00 00 00 04 add\.p gr0,gr4,gr0 - 43d8: R_FRV_FUNCDESC_VALUE \.text - 43dc: 00 00 00 00 add\.p gr0,gr0,gr0 - 43e0: 00 00 00 04 add\.p gr0,gr4,gr0 - 43e0: R_FRV_FUNCDESC_VALUE \.text - 43e4: 00 00 00 00 add\.p gr0,gr0,gr0 - 43e8: 00 00 00 04 add\.p gr0,gr4,gr0 - 43e8: R_FRV_FUNCDESC_VALUE \.text - 43ec: 00 00 00 00 add\.p gr0,gr0,gr0 - 43f0: 00 00 00 04 add\.p gr0,gr4,gr0 - 43f0: R_FRV_FUNCDESC_VALUE \.text - 43f4: 00 00 00 00 add\.p gr0,gr0,gr0 - 43f8: 00 00 00 04 add\.p gr0,gr4,gr0 - 43f8: R_FRV_FUNCDESC_VALUE \.text - 43fc: 00 00 00 00 add\.p gr0,gr0,gr0 - 4400: 00 00 00 04 add\.p gr0,gr4,gr0 - 4400: R_FRV_FUNCDESC_VALUE \.text - 4404: 00 00 00 00 add\.p gr0,gr0,gr0 - 4408: 00 00 00 04 add\.p gr0,gr4,gr0 - 4408: R_FRV_FUNCDESC_VALUE \.text - 440c: 00 00 00 00 add\.p gr0,gr0,gr0 +00004300 <_GLOBAL_OFFSET_TABLE_-0x38>: + 4300: 00 00 00 04 add\.p gr0,gr4,gr0 + 4300: R_FRV_FUNCDESC_VALUE \.text + 4304: 00 00 00 00 add\.p gr0,gr0,gr0 + 4308: 00 00 00 04 add\.p gr0,gr4,gr0 + 4308: R_FRV_FUNCDESC_VALUE \.text + 430c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4310: 00 00 00 04 add\.p gr0,gr4,gr0 + 4310: R_FRV_FUNCDESC_VALUE \.text + 4314: 00 00 00 00 add\.p gr0,gr0,gr0 + 4318: 00 00 00 04 add\.p gr0,gr4,gr0 + 4318: R_FRV_FUNCDESC_VALUE \.text + 431c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4320: 00 00 00 04 add\.p gr0,gr4,gr0 + 4320: R_FRV_FUNCDESC_VALUE \.text + 4324: 00 00 00 00 add\.p gr0,gr0,gr0 + 4328: 00 00 00 04 add\.p gr0,gr4,gr0 + 4328: R_FRV_FUNCDESC_VALUE \.text + 432c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4330: 00 00 00 04 add\.p gr0,gr4,gr0 + 4330: R_FRV_FUNCDESC_VALUE \.text + 4334: 00 00 00 00 add\.p gr0,gr0,gr0 -00004410 <_GLOBAL_OFFSET_TABLE_>: +00004338 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 441c: 00 00 00 10 add\.p gr0,gr16,gr0 - 441c: R_FRV_32 \.got - 4420: 00 00 00 04 add\.p gr0,gr4,gr0 - 4420: R_FRV_32 \.text - 4424: 00 00 00 28 add\.p gr0,gr40,gr0 - 4424: R_FRV_32 \.got - 4428: 00 00 00 20 add\.p gr0,gr32,gr0 - 4428: R_FRV_32 \.got - 442c: 00 00 00 04 add\.p gr0,gr4,gr0 - 442c: R_FRV_32 \.data - 4430: 00 00 00 04 add\.p gr0,gr4,gr0 - 4430: R_FRV_32 \.text - 4434: 00 00 00 04 add\.p gr0,gr4,gr0 - 4434: R_FRV_32 \.text + 4344: 00 00 00 10 add\.p gr0,gr16,gr0 + 4344: R_FRV_32 \.got + 4348: 00 00 00 04 add\.p gr0,gr4,gr0 + 4348: R_FRV_32 \.text + 434c: 00 00 00 28 add\.p gr0,gr40,gr0 + 434c: R_FRV_32 \.got + 4350: 00 00 00 20 add\.p gr0,gr32,gr0 + 4350: R_FRV_32 \.got + 4354: 00 00 00 04 add\.p gr0,gr4,gr0 + 4354: R_FRV_32 \.data + 4358: 00 00 00 04 add\.p gr0,gr4,gr0 + 4358: R_FRV_32 \.text + 435c: 00 00 00 04 add\.p gr0,gr4,gr0 + 435c: R_FRV_32 \.text diff --git a/ld/testsuite/ld-frv/fdpic-shared-local-8.d b/ld/testsuite/ld-frv/fdpic-shared-local-8.d index 8b179e3..b0aeec1 100644 --- a/ld/testsuite/ld-frv/fdpic-shared-local-8.d +++ b/ld/testsuite/ld-frv/fdpic-shared-local-8.d @@ -8,77 +8,77 @@ Disassembly of section \.text: -00000300 <F8>: - 300: 80 3c 00 02 call 308 <GF0\+0x4> +00000228 <F8>: + 228: 80 3c 00 02 call 230 <GF0\+0x4> -00000304 <GF0>: - 304: 80 40 f0 10 addi gr15,16,gr0 - 308: 80 fc 00 14 setlos 0x14,gr0 - 30c: 80 f4 00 24 setlo 0x24,gr0 - 310: 80 f8 00 00 sethi hi\(0x0\),gr0 - 314: 80 40 f0 0c addi gr15,12,gr0 - 318: 80 fc 00 1c setlos 0x1c,gr0 - 31c: 80 f4 00 18 setlo 0x18,gr0 - 320: 80 f8 00 00 sethi hi\(0x0\),gr0 - 324: 80 40 ff f8 addi gr15,-8,gr0 - 328: 80 fc ff f0 setlos 0xfffffff0,gr0 - 32c: 80 f4 ff c8 setlo 0xffc8,gr0 - 330: 80 f8 ff ff sethi 0xffff,gr0 - 334: 80 40 ff 48 addi gr15,-184,gr0 - 338: 80 fc ff 48 setlos 0xffffff48,gr0 - 33c: 80 f4 ff 48 setlo 0xff48,gr0 - 340: 80 f8 ff ff sethi 0xffff,gr0 - 344: 80 f4 00 20 setlo 0x20,gr0 - 348: 80 f8 00 00 sethi hi\(0x0\),gr0 +0000022c <GF0>: + 22c: 80 40 f0 10 addi gr15,16,gr0 + 230: 80 fc 00 14 setlos 0x14,gr0 + 234: 80 f4 00 24 setlo 0x24,gr0 + 238: 80 f8 00 00 sethi hi\(0x0\),gr0 + 23c: 80 40 f0 0c addi gr15,12,gr0 + 240: 80 fc 00 1c setlos 0x1c,gr0 + 244: 80 f4 00 18 setlo 0x18,gr0 + 248: 80 f8 00 00 sethi hi\(0x0\),gr0 + 24c: 80 40 ff f8 addi gr15,-8,gr0 + 250: 80 fc ff f0 setlos 0xfffffff0,gr0 + 254: 80 f4 ff c8 setlo 0xffc8,gr0 + 258: 80 f8 ff ff sethi 0xffff,gr0 + 25c: 80 40 ff c0 addi gr15,-64,gr0 + 260: 80 fc ff c0 setlos 0xffffffc0,gr0 + 264: 80 f4 ff c0 setlo 0xffc0,gr0 + 268: 80 f8 ff ff sethi 0xffff,gr0 + 26c: 80 f4 00 20 setlo 0x20,gr0 + 270: 80 f8 00 00 sethi hi\(0x0\),gr0 Disassembly of section \.data: -00004350 <D8>: - 4350: 00 00 00 08 add\.p gr0,gr8,gr0 - 4350: R_FRV_32 \.data +000042f0 <D8>: + 42f0: 00 00 00 08 add\.p gr0,gr8,gr0 + 42f0: R_FRV_32 \.data -00004354 <GD0>: - 4354: 00 00 00 10 add\.p gr0,gr16,gr0 - 4354: R_FRV_32 \.got - 4358: 00 00 00 08 add\.p gr0,gr8,gr0 - 4358: R_FRV_32 \.text +000042f4 <GD0>: + 42f4: 00 00 00 10 add\.p gr0,gr16,gr0 + 42f4: R_FRV_32 \.got + 42f8: 00 00 00 08 add\.p gr0,gr8,gr0 + 42f8: R_FRV_32 \.text Disassembly of section \.got: -000043d8 <_GLOBAL_OFFSET_TABLE_-0x38>: - 43d8: 00 00 00 08 add\.p gr0,gr8,gr0 - 43d8: R_FRV_FUNCDESC_VALUE \.text - 43dc: 00 00 00 00 add\.p gr0,gr0,gr0 - 43e0: 00 00 00 08 add\.p gr0,gr8,gr0 - 43e0: R_FRV_FUNCDESC_VALUE \.text - 43e4: 00 00 00 00 add\.p gr0,gr0,gr0 - 43e8: 00 00 00 08 add\.p gr0,gr8,gr0 - 43e8: R_FRV_FUNCDESC_VALUE \.text - 43ec: 00 00 00 00 add\.p gr0,gr0,gr0 - 43f0: 00 00 00 08 add\.p gr0,gr8,gr0 - 43f0: R_FRV_FUNCDESC_VALUE \.text - 43f4: 00 00 00 00 add\.p gr0,gr0,gr0 - 43f8: 00 00 00 08 add\.p gr0,gr8,gr0 - 43f8: R_FRV_FUNCDESC_VALUE \.text - 43fc: 00 00 00 00 add\.p gr0,gr0,gr0 - 4400: 00 00 00 08 add\.p gr0,gr8,gr0 - 4400: R_FRV_FUNCDESC_VALUE \.text - 4404: 00 00 00 00 add\.p gr0,gr0,gr0 - 4408: 00 00 00 08 add\.p gr0,gr8,gr0 - 4408: R_FRV_FUNCDESC_VALUE \.text - 440c: 00 00 00 00 add\.p gr0,gr0,gr0 +00004300 <_GLOBAL_OFFSET_TABLE_-0x38>: + 4300: 00 00 00 08 add\.p gr0,gr8,gr0 + 4300: R_FRV_FUNCDESC_VALUE \.text + 4304: 00 00 00 00 add\.p gr0,gr0,gr0 + 4308: 00 00 00 08 add\.p gr0,gr8,gr0 + 4308: R_FRV_FUNCDESC_VALUE \.text + 430c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4310: 00 00 00 08 add\.p gr0,gr8,gr0 + 4310: R_FRV_FUNCDESC_VALUE \.text + 4314: 00 00 00 00 add\.p gr0,gr0,gr0 + 4318: 00 00 00 08 add\.p gr0,gr8,gr0 + 4318: R_FRV_FUNCDESC_VALUE \.text + 431c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4320: 00 00 00 08 add\.p gr0,gr8,gr0 + 4320: R_FRV_FUNCDESC_VALUE \.text + 4324: 00 00 00 00 add\.p gr0,gr0,gr0 + 4328: 00 00 00 08 add\.p gr0,gr8,gr0 + 4328: R_FRV_FUNCDESC_VALUE \.text + 432c: 00 00 00 00 add\.p gr0,gr0,gr0 + 4330: 00 00 00 08 add\.p gr0,gr8,gr0 + 4330: R_FRV_FUNCDESC_VALUE \.text + 4334: 00 00 00 00 add\.p gr0,gr0,gr0 -00004410 <_GLOBAL_OFFSET_TABLE_>: +00004338 <_GLOBAL_OFFSET_TABLE_>: \.\.\. - 441c: 00 00 00 08 add\.p gr0,gr8,gr0 - 441c: R_FRV_32 \.got - 4420: 00 00 00 08 add\.p gr0,gr8,gr0 - 4420: R_FRV_32 \.text - 4424: 00 00 00 08 add\.p gr0,gr8,gr0 - 4424: R_FRV_32 \.text - 4428: 00 00 00 20 add\.p gr0,gr32,gr0 - 4428: R_FRV_32 \.got - 442c: 00 00 00 18 add\.p gr0,gr24,gr0 - 442c: R_FRV_32 \.got - 4430: 00 00 00 08 add\.p gr0,gr8,gr0 - 4430: R_FRV_32 \.data - 4434: 00 00 00 08 add\.p gr0,gr8,gr0 - 4434: R_FRV_32 \.text + 4344: 00 00 00 08 add\.p gr0,gr8,gr0 + 4344: R_FRV_32 \.got + 4348: 00 00 00 08 add\.p gr0,gr8,gr0 + 4348: R_FRV_32 \.text + 434c: 00 00 00 08 add\.p gr0,gr8,gr0 + 434c: R_FRV_32 \.text + 4350: 00 00 00 20 add\.p gr0,gr32,gr0 + 4350: R_FRV_32 \.got + 4354: 00 00 00 18 add\.p gr0,gr24,gr0 + 4354: R_FRV_32 \.got + 4358: 00 00 00 08 add\.p gr0,gr8,gr0 + 4358: R_FRV_32 \.data + 435c: 00 00 00 08 add\.p gr0,gr8,gr0 + 435c: R_FRV_32 \.text |