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| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2011-12-07 16:46:35 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2011-12-07 16:46:35 +0000 |
| commit | ad6cec4372cbd9c17151f4b6b84759a2fb30f2b2 (patch) | |
| tree | d5ec56812b705da8f66e10985d40956d05319691 | |
| parent | 1b11b49fe420e2d2699f1763ab51aa7a9f26d63a (diff) | |
| download | binutils-ad6cec4372cbd9c17151f4b6b84759a2fb30f2b2.zip binutils-ad6cec4372cbd9c17151f4b6b84759a2fb30f2b2.tar.gz binutils-ad6cec4372cbd9c17151f4b6b84759a2fb30f2b2.tar.bz2 | |
* gas/config/tc-arm.c (ARM_IT_MAX_OPERANDS): New define.
(arm_it): Use ARM_IT_MAX_OPERANDS.
(neon_select_shape): Ensure we have matched all operands.
* gas/testsuite/gas/arm/neon-suffix-bad.l: Add testcase.
* gas/testsuite/gas/arm/neon-suffix-bad.s: Likewise.
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 9 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/neon-suffix-bad.l | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/neon-suffix-bad.s | 3 |
5 files changed, 23 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index cc62920..d52c5b6 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2011-11-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + * config/tc-arm.c (ARM_IT_MAX_OPERANDS): New define. + (arm_it): Use ARM_IT_MAX_OPERANDS. + (neon_select_shape): Ensure we have matched all operands. + +2011-11-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + * config/tc-arm.c (parse_neon_mov): Update which_operand correctly. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 52a9030..064267e 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -351,6 +351,9 @@ enum it_instruction_type IT_INSN /* The IT insn has been parsed. */ }; +/* The maximum number of operands we need. */ +#define ARM_IT_MAX_OPERANDS 6 + struct arm_it { const char * error; @@ -402,7 +405,7 @@ struct arm_it unsigned negative : 1; /* Index register was negated. */ unsigned shifted : 1; /* Shift applied to operation. */ unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ - } operands[6]; + } operands[ARM_IT_MAX_OPERANDS]; }; static struct arm_it inst; @@ -12415,7 +12418,9 @@ neon_select_shape (enum neon_shape shape, ...) if (!matches) break; } - if (matches) + if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) + /* We've matched all the entries in the shape table, and we don't + have any left over operands which have not been matched. */ break; } diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 1879288..8d6e8b6 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2011-11-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> + + * gas/arm/neon-suffix-bad.l: Add testcase. + * gas/arm/neon-suffix-bad.s: Likewise. + 2011-12-05 Richard Earnshaw <rearnsha@arm.com> * gas/arm/attr-any-armv4t.d: New test. diff --git a/gas/testsuite/gas/arm/neon-suffix-bad.l b/gas/testsuite/gas/arm/neon-suffix-bad.l index 4c44f6b..091429d 100644 --- a/gas/testsuite/gas/arm/neon-suffix-bad.l +++ b/gas/testsuite/gas/arm/neon-suffix-bad.l @@ -2,6 +2,8 @@ [^:]*:3: Error: invalid neon suffix for non neon instruction [^:]*:4: Error: invalid neon suffix for non neon instruction [^:]*:5: Error: invalid neon suffix for non neon instruction -[^:]*:8: Error: invalid neon suffix for non neon instruction +[^:]*:6: Error: invalid instruction shape -- `vcvt.f64.s32 d0,s0,#11' [^:]*:9: Error: invalid neon suffix for non neon instruction [^:]*:10: Error: invalid neon suffix for non neon instruction +[^:]*:11: Error: invalid neon suffix for non neon instruction +[^:]*:12: Error: invalid instruction shape -- `vcvt.f64.s32 d0,s0,#11' diff --git a/gas/testsuite/gas/arm/neon-suffix-bad.s b/gas/testsuite/gas/arm/neon-suffix-bad.s index 288dba7..20c60fe 100644 --- a/gas/testsuite/gas/arm/neon-suffix-bad.s +++ b/gas/testsuite/gas/arm/neon-suffix-bad.s @@ -3,10 +3,11 @@ add.f32 r0, r0, r0 faddd.f32 d0, d0, d0 faddd.f64 d0, d0, d0 +vcvt.f64.s32 d0, s0, #11 .thumb add.f32 r0, r0, r0 faddd.f32 d0, d0, d0 faddd.f64 d0, d0, d0 - +vcvt.f64.s32 d0, s0, #11 |