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author | Cui, Lili <lili.cui@intel.com> | 2024-10-15 14:13:33 +0800 |
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committer | Cui, Lili <lili.cui@intel.com> | 2024-10-15 14:17:57 +0800 |
commit | 9c5b0ee4d5633664733afddfe79ca8fb75cce5cd (patch) | |
tree | 63d62740a0f637eb52ee0196d308cc9717ce0c89 | |
parent | 990c7d444ce31291229bd2de9261b763bad14ab7 (diff) | |
download | binutils-9c5b0ee4d5633664733afddfe79ca8fb75cce5cd.zip binutils-9c5b0ee4d5633664733afddfe79ca8fb75cce5cd.tar.gz binutils-9c5b0ee4d5633664733afddfe79ca8fb75cce5cd.tar.bz2 |
x86: Refine instruction check in x86_check_tls_relocation
gas/ChangeLog:
* config/tc-i386.c
(x86_check_tls_relocation): Refine instruction check.
-rw-r--r-- | gas/config/tc-i386.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index cdefde0..cfab10d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -6747,9 +6747,10 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_type) && i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov) return x86_tls_error_insn; - if (i.op[1].regs->reg_type.bitfield.class != Reg - || i.op[0].regs->reg_type.bitfield.class - || i.imm_operands) + if (i.imm_operands + || i.disp_operands != 1 + || i.reg_operands != 1 + || i.types[1].bitfield.class != Reg) return x86_tls_error_opcode; if (!i.base_reg) return x86_tls_error_no_base_reg; @@ -6769,9 +6770,10 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_type) */ if (i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov) return x86_tls_error_insn; - if (i.op[1].regs->reg_type.bitfield.class != Reg - || i.op[0].regs->reg_type.bitfield.class - || i.imm_operands) + if (i.imm_operands + || i.disp_operands != 1 + || i.reg_operands != 1 + || i.types[1].bitfield.class != Reg) return x86_tls_error_opcode; if (i.base_reg || i.index_reg) return x86_tls_error_require_no_base_index_reg; @@ -6789,10 +6791,9 @@ x86_check_tls_relocation (enum bfd_reloc_code_real r_type) */ if (i.tm.mnem_off != MN_add && i.tm.mnem_off != MN_mov) return x86_tls_error_insn; - if (i.op[i.operands - 1].regs->reg_type.bitfield.class != Reg - || (i.op[0].regs->reg_type.bitfield.class - && i.tm.opcode_modifier.vexvvvv != VexVVVV_DST) - || i.imm_operands) + if (i.imm_operands + || i.disp_operands != 1 + || i.types[i.operands - 1].bitfield.class != Reg) return x86_tls_error_opcode; if (!i.base_reg) return x86_tls_error_no_base_reg; |