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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-02 23:50:27 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-03 00:01:31 +0000 |
| commit | 92f46037a0f672d1480f754f76a9bfa0334d099c (patch) | |
| tree | 4adfd6c80389f5dc1b0ae0f7f3834bf7836c45aa | |
| parent | 4b177a76d5b759ba631568fb69e8750e99b43647 (diff) | |
| download | binutils-92f46037a0f672d1480f754f76a9bfa0334d099c.zip binutils-92f46037a0f672d1480f754f76a9bfa0334d099c.tar.gz binutils-92f46037a0f672d1480f754f76a9bfa0334d099c.tar.bz2 | |
RISC-V: Imply 'Zicsr' from 'Zve32x'
Further clarification is made so that 'Zve32x' implies 'Zicsr' (the same
implication is already implemented in LLVM).
See related issue (the author raised) on the vector specification:
<https://github.com/riscv/riscv-v-spec/issues/908>
and its resolution:
<https://github.com/riscv/riscv-v-spec/issues/909>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zve32x' -> 'Zicsr'.
| -rw-r--r-- | bfd/elfxx-riscv.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ba51657..2ce95d9 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1121,6 +1121,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zve64x", "zve32x", check_implicit_always}, {"zve64x", "zvl64b", check_implicit_always}, {"zve32x", "zvl32b", check_implicit_always}, + {"zve32x", "zicsr", check_implicit_always}, {"zvl65536b", "zvl32768b", check_implicit_always}, {"zvl32768b", "zvl16384b", check_implicit_always}, {"zvl16384b", "zvl8192b", check_implicit_always}, |