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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-12-13 15:04:15 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:40 +0000 |
| commit | 92d8946670571118cccdbcd36d35300af33da4af (patch) | |
| tree | 1668317a29d3bf61812d666db20bf7a157cb99b9 | |
| parent | 5517af829887ba3b19a3f372b6b60e8098bdfa29 (diff) | |
| download | binutils-92d8946670571118cccdbcd36d35300af33da4af.zip binutils-92d8946670571118cccdbcd36d35300af33da4af.tar.gz binutils-92d8946670571118cccdbcd36d35300af33da4af.tar.bz2 | |
aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macros
Some 128-bit system operations (mrrs, msrr, tlbip, and sysp) take two
qualified operands and one of unqualified type (e.g. system register
name, tlbip operation). This creates the need for adequate qualifiers
to handle this.
This patch therefore introduces the `QL_SRC_X2' and `QL_DST_X2' qualifier
specifiers, which expand to `QLF3(NIL,X,X)' and `QLF3(X,X,NIL)',
respectively.
| -rw-r--r-- | opcodes/aarch64-tbl.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 3f1b388..ec14e4b 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -52,12 +52,24 @@ QLF2(NIL,X), \ } +/* e.g. MSRR <systemreg>, <Xt>, <Xt2>. */ +#define QL_SRC_X2 \ +{ \ + QLF3(NIL,X,X), \ +} + /* e.g. MRS <Xt>, <systemreg>. */ #define QL_DST_X \ { \ QLF2(X,NIL), \ } +/* e.g. MRRS <Xt>, <Xt2>, <systemreg>. */ +#define QL_DST_X2 \ +{ \ + QLF3(X,X,NIL), \ +} + /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ #define QL_SYS \ { \ |