diff options
author | Richard Earnshaw <rearnsha@arm.com> | 2024-06-04 12:56:26 +0100 |
---|---|---|
committer | Richard Earnshaw <rearnsha@arm.com> | 2024-06-05 17:45:45 +0100 |
commit | 791715659986588b384045dc9248a868244ead80 (patch) | |
tree | eb4961c33552282a85a010d9d669fa2d951d5a44 | |
parent | 01613db7875f494a09327d19cfcd2d4f976be416 (diff) | |
download | binutils-791715659986588b384045dc9248a868244ead80.zip binutils-791715659986588b384045dc9248a868244ead80.tar.gz binutils-791715659986588b384045dc9248a868244ead80.tar.bz2 |
arm: remove disassembly support for the FPA co-processor
Remove the FPA support from the disassembler. This entails a couple
of testsuite fixes where we were (probably incorrectly) disassembling
a generic co-processor instruction using the legacy FPA opcodes.
-rw-r--r-- | gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d | 6 | ||||
-rw-r--r-- | include/opcode/arm.h | 7 | ||||
-rw-r--r-- | opcodes/arm-dis.c | 197 |
4 files changed, 10 insertions, 206 deletions
diff --git a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d index 0d88359..9cc6a96 100644 --- a/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d +++ b/gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d @@ -8,10 +8,10 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> ee421103 dvfs f1, f2, f3 +0+000 <[^>]*> ee421103 cdp 1, 4, cr1, cr2, cr3, \{0\} 0+004 <[^>]*> 0e3414a5 cdpeq 4, 3, cr1, cr4, cr5, \{5\} 0+008 <[^>]*> ed939500 ldc 5, cr9, \[r3\] -0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\] +0+00c <[^>]*> edd1e108 ldcl 1, cr14, \[r1, #32\] 0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.* 0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.* 0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] @ .* <foo> @@ -19,7 +19,7 @@ Disassembly of section .text: 0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\] 0+024 <[^>]*> 0da2c419 stceq 4, cr12, \[r2, #100\]! @.* 0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.* -0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] @ .* <bar> +0+02c <[^>]*> ed0f7101 stc 1, cr7, \[pc, #-4\] @ .* <bar> 0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\} 0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\} 0+038 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\} diff --git a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d index 243610f..6e55633 100644 --- a/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d +++ b/gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d @@ -8,11 +8,11 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> ee42 1103 dvfs f1, f2, f3 +0+000 <[^>]*> ee42 1103 cdp 1, 4, cr1, cr2, cr3, \{0\} 0+004 <[^>]*> [^ ]* it eq 0+006 <[^>]*> ee34 14a5 cdpeq 4, 3, cr1, cr4, cr5, \{5\} 0+00a <[^>]*> ed93 9500 ldc 5, cr9, \[r3\] -0+00e <[^>]*> edd1 e108 ldfp f6, \[r1, #32\] +0+00e <[^>]*> edd1 e108 ldcl 1, cr14, \[r1, #32\] 0+012 <[^>]*> [^ ]* ite mi 0+014 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.* 0+018 <[^>]*> ecf3 1710 ldclpl 7, cr1, \[r3\], #64.* @@ -23,7 +23,7 @@ Disassembly of section .text: 0+02a <[^>]*> eda2 c419 stceq 4, cr12, \[r2, #100\]! @.* 0+02e <[^>]*> [^ ]* it cc 0+030 <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.* -0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] @ .* <bar> +0+034 <[^>]*> ed8f 7100 stc 1, cr7, \[pc\] @ .* <bar> 0+038 <[^>]*> ee71 5212 mrc 2, 3, r5, cr1, cr2, \{0\} 0+03c <[^>]*> [^ ]* it ge 0+03e <[^>]*> eeb1 f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\} diff --git a/include/opcode/arm.h b/include/opcode/arm.h index ddc199e..a89c215 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -105,8 +105,8 @@ coprocessor version 2. */ #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ -#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ -#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ +/* unused 0x40000000 */ +/* unused 0x20000000 */ /* unused 0x10000000 */ #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ @@ -244,7 +244,6 @@ | FPU_VFP_EXT_V3 \ | FPU_NEON_EXT_V1 \ | FPU_VFP_EXT_D32) -#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) /* Deprecated. */ #define FPU_ARCH_SOFTVFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) @@ -404,7 +403,7 @@ #define ARM_ARCH_UNKNOWN ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, -1) /* Machine type is unknown. */ #define ARM_ANY ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, 0) /* Any basic core. */ #define FPU_ANY ARM_FEATURE_COPROC (-1 & ~(ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)) /* Any FPU. */ -#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD) +#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD) /* Extensions containing some Thumb-2 instructions. If any is present, Thumb ISA is Thumb-2. */ #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7 \ diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index b63fadd..480e4c2 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -405,16 +405,11 @@ struct opcode16 %q print shifter argument %u print condition code (unconditional in ARM mode, UNPREDICTABLE if not AL in Thumb) - %A print address for ldc/stc/ldf/stf instruction + %A print address for ldc/stc instruction %B print vstm/vldm register list %C print vscclrm register list - %I print cirrus signed shift immediate: bits 0..3|4..6 %J print register for VLDR instruction %K print address for VLDR instruction - %F print the COUNT field of a LFM/SFM instruction. - %P print floating point precision in arithmetic insn - %Q print floating point precision in ldf/stf insn - %R print floating point rounding mode %<bitfield>c print as a condition code (for vsel) %<bitfield>r print as an ARM register @@ -424,8 +419,6 @@ struct opcode16 %<bitfield>k print immediate for VFPv3 conversion instruction %<bitfield>x print the bitfield in hex %<bitfield>X print the bitfield as 1 hex digit without leading "0x" - %<bitfield>f print a floating point constant if >7 else a - floating point register %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us %<bitfield>g print as an iWMMXt 64-bit register %<bitfield>G print as an iWMMXt general purpose or control register @@ -707,94 +700,6 @@ static const struct sopcode32 coprocessor_opcodes[] = {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_END, 0, "" }, - /* Floating point coprocessor (FPA) instructions. */ - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), - 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), - 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, - {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), - 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, - /* Armv8.1-M Mainline instructions. */ {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"}, @@ -5011,9 +4916,6 @@ static const char *const arm_conditional[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; -static const char *const arm_fp_const[] = -{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; - static const char *const arm_shift[] = {"lsl", "lsr", "asr", "ror"}; @@ -8299,25 +8201,6 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes, arm_conditional[cond]); break; - case 'I': - /* Print a Cirrus/DSP shift immediate. */ - /* Immediates are 7bit signed ints with bits 0..3 in - bits 0..3 of opcode and bits 4..6 in bits 5..7 - of opcode. */ - { - int imm; - - imm = (given & 0xf) | ((given & 0xe0) >> 1); - - /* Is ``imm'' a negative number? */ - if (imm & 0x40) - imm -= 0x80; - - func (stream, dis_style_immediate, "%d", imm); - } - - break; - case 'J': { unsigned long regno @@ -8351,76 +8234,6 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes, } break; - case 'F': - switch (given & 0x00408000) - { - case 0: - func (stream, dis_style_immediate, "4"); - break; - case 0x8000: - func (stream, dis_style_immediate, "1"); - break; - case 0x00400000: - func (stream, dis_style_immediate, "2"); - break; - default: - func (stream, dis_style_immediate, "3"); - } - break; - - case 'P': - switch (given & 0x00080080) - { - case 0: - func (stream, dis_style_mnemonic, "s"); - break; - case 0x80: - func (stream, dis_style_mnemonic, "d"); - break; - case 0x00080000: - func (stream, dis_style_mnemonic, "e"); - break; - default: - func (stream, dis_style_text, _("<illegal precision>")); - break; - } - break; - - case 'Q': - switch (given & 0x00408000) - { - case 0: - func (stream, dis_style_mnemonic, "s"); - break; - case 0x8000: - func (stream, dis_style_mnemonic, "d"); - break; - case 0x00400000: - func (stream, dis_style_mnemonic, "e"); - break; - default: - func (stream, dis_style_mnemonic, "p"); - break; - } - break; - - case 'R': - switch (given & 0x60) - { - case 0: - break; - case 0x20: - func (stream, dis_style_mnemonic, "p"); - break; - case 0x40: - func (stream, dis_style_mnemonic, "m"); - break; - default: - func (stream, dis_style_mnemonic, "z"); - break; - } - break; - case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { @@ -8517,14 +8330,6 @@ print_insn_coprocessor_1 (const struct sopcode32 *opcodes, } break; - case 'f': - if (value > 7) - func (stream, dis_style_immediate, "#%s", - arm_fp_const[value & 7]); - else - func (stream, dis_style_register, "f%ld", value); - break; - case 'w': if (width == 2) func (stream, dis_style_mnemonic, "%s", |