diff options
author | Kito Cheng <kito.cheng@sifive.com> | 2025-01-21 22:07:25 +0800 |
---|---|---|
committer | Nelson Chu <nelson@rivosinc.com> | 2025-03-03 11:47:23 +0800 |
commit | 56a0188548edc605e7e87906822a186c8ce822e1 (patch) | |
tree | 709dd3928dc126d6c953f07f3e98785055c7d677 | |
parent | ade87b8e6293f146f754629101cf4e367aec5da9 (diff) | |
download | binutils-56a0188548edc605e7e87906822a186c8ce822e1.zip binutils-56a0188548edc605e7e87906822a186c8ce822e1.tar.gz binutils-56a0188548edc605e7e87906822a186c8ce822e1.tar.bz2 |
RISC-V: Support ssqosid extension with version 1.0.
It only add one new CSR: `srmcfg`.
Ref: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
-rw-r--r-- | bfd/elfxx-riscv.c | 1 | ||||
-rw-r--r-- | gas/config/tc-riscv.c | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/csr-version-1p10.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/csr-version-1p10.l | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/csr-version-1p11.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/csr-version-1p11.l | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/csr-version-1p12.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/csr-version-1p12.l | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/csr.s | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/march-help.l | 1 | ||||
-rw-r--r-- | include/opcode/riscv-opc.h | 4 |
11 files changed, 31 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index c9e4b03..fd2cb74 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1476,6 +1476,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] = {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssqosid", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index ca269bd..bd8b020 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -105,6 +105,7 @@ enum riscv_csr_class CSR_CLASS_SSTC_32, /* Sstc RV32 only */ CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */ CSR_CLASS_SSCTR, /* Ssctr */ + CSR_CLASS_SSQOSID, /* Ssqosid */ CSR_CLASS_XTHEADVECTOR, /* xtheadvector only */ }; @@ -1166,6 +1167,9 @@ riscv_csr_address (const char *csr_name, case CSR_CLASS_XTHEADVECTOR: extension = "xtheadvector"; break; + case CSR_CLASS_SSQOSID: + extension = "ssqosid"; + break; default: as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class); } diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d index 0729795..6896e7b 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.d +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d @@ -933,3 +933,5 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 [ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt [ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1 +[ ]+[0-9a-f]+:[ ]+18102573[ ]+csrr[ ]+a0,srmcfg +[ ]+[0-9a-f]+:[ ]+18159073[ ]+csrw[ ]+srmcfg,a1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l index 2427ba9..46d1e4e 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.l +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l @@ -1717,3 +1717,7 @@ .*Info: macro .* .*Warning: invalid CSR `jvt', needs `zcmt' extension .*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d index 70cafb8..308140a 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.d +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d @@ -933,3 +933,5 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 [ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt [ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1 +[ ]+[0-9a-f]+:[ ]+18102573[ ]+csrr[ ]+a0,srmcfg +[ ]+[0-9a-f]+:[ ]+18159073[ ]+csrw[ ]+srmcfg,a1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l index aeec089..9e813e2 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.l +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l @@ -1713,3 +1713,7 @@ .*Info: macro .* .*Warning: invalid CSR `jvt', needs `zcmt' extension .*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d index daf79f4..5fe3316 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.d +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d @@ -933,3 +933,5 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 [ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt [ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1 +[ ]+[0-9a-f]+:[ ]+18102573[ ]+csrr[ ]+a0,srmcfg +[ ]+[0-9a-f]+:[ ]+18159073[ ]+csrw[ ]+srmcfg,a1 diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l index 3710da9..ff60ec0 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.l +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l @@ -1477,3 +1477,7 @@ .*Info: macro .* .*Warning: invalid CSR `jvt', needs `zcmt' extension .*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* +.*Warning: invalid CSR `srmcfg', needs `ssqosid' extension +.*Info: macro .* diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s index 44fc1e7..6244bd7 100644 --- a/gas/testsuite/gas/riscv/csr.s +++ b/gas/testsuite/gas/riscv/csr.s @@ -541,3 +541,6 @@ # Zcmt csr jvt + + # Ssqosid + csr srmcfg diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index f92c98f..b7975ff 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -139,6 +139,7 @@ All available -march extensions for RISC-V: svinval 1.0 svnapot 1.0 svpbmt 1.0 + ssqosid 1.0 xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 71ad7ff..24af3ac 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -4254,6 +4254,8 @@ #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 #define CSR_VLENB 0xc22 +/* Ssqosid CSR addresses. */ +#define CSR_SRMCFG 0x181 #endif /* RISCV_ENCODING_H */ #ifdef DECLARE_INSN DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) @@ -5393,6 +5395,8 @@ DECLARE_CSR(vcsr, CSR_VCSR, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_N DECLARE_CSR(vl, CSR_VL, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vtype, CSR_VTYPE, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vlenb, CSR_VLENB, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Ssqosid CSR. */ +DECLARE_CSR(srmcfg, CSR_SRMCFG, CSR_CLASS_SSQOSID, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) #endif /* DECLARE_CSR */ #ifdef DECLARE_CSR_ALIAS DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) |