diff options
author | Doug Evans <dje@google.com> | 2003-04-22 18:50:55 +0000 |
---|---|---|
committer | Doug Evans <dje@google.com> | 2003-04-22 18:50:55 +0000 |
commit | 390ff83f7224cb7033b7e2dd23f268419a81fda4 (patch) | |
tree | f2e49b4ef42318347b55d95267f06cc4233ff3da | |
parent | 4252f1df1a32177acb7653e9c38bfb909f2a6668 (diff) | |
download | binutils-390ff83f7224cb7033b7e2dd23f268419a81fda4.zip binutils-390ff83f7224cb7033b7e2dd23f268419a81fda4.tar.gz binutils-390ff83f7224cb7033b7e2dd23f268419a81fda4.tar.bz2 |
* fr30-desc.c,fr30-desc.h,fr30-opc.c,fr30-opc.h: Regenerate.
* frv-desc.c,frv-desc.h,frv-opc.c,frv-opc.h: Regenerate.
* ip2k-desc.c,ip2k-desc.h,ip2k-opc.c,ip2k-opc.h: Regenerate.
* m32r-desc.c,m32r-desc.h,m32r-opc.c,m32r-opc.h: Regenerate.
* m32r-opinst.c: Regenerate.
* openrisc-desc.c,openrisc-desc.h,openrisc-opc.c,openrisc-opc.h: Regenerate.
* xstormy16-desc.c,xstormy16-desc.h,xstormy16-opc.c,xstormy16-opc.h: Regenerate.
-rw-r--r-- | opcodes/ChangeLog | 10 | ||||
-rw-r--r-- | opcodes/fr30-desc.c | 2 | ||||
-rw-r--r-- | opcodes/fr30-desc.h | 2 | ||||
-rw-r--r-- | opcodes/fr30-opc.c | 2 | ||||
-rw-r--r-- | opcodes/fr30-opc.h | 2 | ||||
-rw-r--r-- | opcodes/frv-desc.c | 149 | ||||
-rw-r--r-- | opcodes/frv-desc.h | 2 | ||||
-rw-r--r-- | opcodes/frv-opc.c | 2 | ||||
-rw-r--r-- | opcodes/frv-opc.h | 2 | ||||
-rw-r--r-- | opcodes/ip2k-desc.c | 20 | ||||
-rw-r--r-- | opcodes/ip2k-desc.h | 2 | ||||
-rw-r--r-- | opcodes/ip2k-opc.c | 2 | ||||
-rw-r--r-- | opcodes/ip2k-opc.h | 2 | ||||
-rw-r--r-- | opcodes/m32r-desc.c | 48 | ||||
-rw-r--r-- | opcodes/m32r-desc.h | 2 | ||||
-rw-r--r-- | opcodes/m32r-opc.c | 2 | ||||
-rw-r--r-- | opcodes/m32r-opc.h | 2 | ||||
-rw-r--r-- | opcodes/m32r-opinst.c | 2 | ||||
-rw-r--r-- | opcodes/openrisc-desc.c | 33 | ||||
-rw-r--r-- | opcodes/openrisc-desc.h | 2 | ||||
-rw-r--r-- | opcodes/openrisc-opc.c | 2 | ||||
-rw-r--r-- | opcodes/openrisc-opc.h | 2 | ||||
-rw-r--r-- | opcodes/xstormy16-desc.c | 60 | ||||
-rw-r--r-- | opcodes/xstormy16-desc.h | 2 | ||||
-rw-r--r-- | opcodes/xstormy16-opc.c | 8 | ||||
-rw-r--r-- | opcodes/xstormy16-opc.h | 7 |
26 files changed, 199 insertions, 172 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8148ca9..9ff6e84 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2003-04-22 Doug Evans <dje@sebabeach.org> + + * fr30-desc.c,fr30-desc.h,fr30-opc.c,fr30-opc.h: Regenerate. + * frv-desc.c,frv-desc.h,frv-opc.c,frv-opc.h: Regenerate. + * ip2k-desc.c,ip2k-desc.h,ip2k-opc.c,ip2k-opc.h: Regenerate. + * m32r-desc.c,m32r-desc.h,m32r-opc.c,m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + * openrisc-desc.c,openrisc-desc.h,openrisc-opc.c,openrisc-opc.h: Regenerate. + * xstormy16-desc.c,xstormy16-desc.h,xstormy16-opc.c,xstormy16-opc.h: Regenerate. + 2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com> * h8500-opc.c: Replace occurrances of 'Hitachi' with 'Renesas'. diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c index a263da7..01d896f 100644 --- a/opcodes/fr30-desc.c +++ b/opcodes/fr30-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h index 41de0bb..6be96d9 100644 --- a/opcodes/fr30-desc.h +++ b/opcodes/fr30-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c index b47cbcd..34c5156 100644 --- a/opcodes/fr30-opc.c +++ b/opcodes/fr30-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h index 2b89a90..bfa2427 100644 --- a/opcodes/fr30-opc.h +++ b/opcodes/fr30-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c index 54bed6b..5fac77a 100644 --- a/opcodes/frv-desc.c +++ b/opcodes/frv-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -1826,6 +1826,7 @@ const CGEN_IFLD frv_cgen_ifld_table[] = { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } } }, { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } }, { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } }, { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } }, @@ -1838,9 +1839,11 @@ const CGEN_IFLD frv_cgen_ifld_table[] = { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } } }, + { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, @@ -1890,20 +1893,20 @@ const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] = { - { 0, { (const PTR) &frv_cgen_ifld_table[46] } }, - { 0, { (const PTR) &frv_cgen_ifld_table[47] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_H] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_L] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] = { - { 0, { (const PTR) &frv_cgen_ifld_table[58] } }, - { 0, { (const PTR) &frv_cgen_ifld_table[59] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_H] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_L] } }, { 0, { (const PTR) 0 } } }; const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] = { - { 0, { (const PTR) &frv_cgen_ifld_table[61] } }, - { 0, { (const PTR) &frv_cgen_ifld_table[62] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELH6] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELL18] } }, { 0, { (const PTR) 0 } } }; @@ -1924,247 +1927,247 @@ const CGEN_OPERAND frv_cgen_operand_table[] = { /* pc: program counter */ { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0, - { 0, { (const PTR) &frv_cgen_ifld_table[0] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* pack: packing bit */ { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[2] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } }, { 0, { (1<<MACH_BASE) } } }, /* GRi: source register 1 */ { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[8] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } }, { 0, { (1<<MACH_BASE) } } }, /* GRj: source register 2 */ { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[9] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } }, { 0, { (1<<MACH_BASE) } } }, /* GRk: destination register */ { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[10] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, { 0, { (1<<MACH_BASE) } } }, /* GRkhi: destination register */ { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[10] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, { 0, { (1<<MACH_BASE) } } }, /* GRklo: destination register */ { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[10] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, { 0, { (1<<MACH_BASE) } } }, /* GRdoublek: destination register */ { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[10] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, { 0, { (1<<MACH_BASE) } } }, /* ACC40Si: signed accumulator */ { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[19] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } }, { 0, { (1<<MACH_BASE) } } }, /* ACC40Ui: unsigned accumulator */ { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[20] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } }, { 0, { (1<<MACH_BASE) } } }, /* ACC40Sk: target accumulator */ { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[21] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } }, { 0, { (1<<MACH_BASE) } } }, /* ACC40Uk: target accumulator */ { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[22] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } }, { 0, { (1<<MACH_BASE) } } }, /* ACCGi: source register */ { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[17] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } }, { 0, { (1<<MACH_BASE) } } }, /* ACCGk: target register */ { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[18] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } }, { 0, { (1<<MACH_BASE) } } }, /* CPRi: source register */ { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[14] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } }, { 0, { (1<<MACH_FRV) } } }, /* CPRj: source register */ { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[15] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } }, { 0, { (1<<MACH_FRV) } } }, /* CPRk: destination register */ { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[16] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } }, { 0, { (1<<MACH_FRV) } } }, /* CPRdoublek: destination register */ { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[16] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } }, { 0, { (1<<MACH_FRV) } } }, /* FRinti: source register 1 */ { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[11] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, { 0, { (1<<MACH_BASE) } } }, /* FRintj: source register 2 */ { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[12] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, { 0, { (1<<MACH_BASE) } } }, /* FRintk: target register */ { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[13] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, { 0, { (1<<MACH_BASE) } } }, /* FRi: source register 1 */ { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[11] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, { 0, { (1<<MACH_BASE) } } }, /* FRj: source register 2 */ { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[12] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, { 0, { (1<<MACH_BASE) } } }, /* FRk: destination register */ { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[13] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, { 0, { (1<<MACH_BASE) } } }, /* FRkhi: destination register */ { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[13] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, { 0, { (1<<MACH_BASE) } } }, /* FRklo: destination register */ { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[13] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, { 0, { (1<<MACH_BASE) } } }, /* FRdoublei: source register 1 */ { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[11] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, { 0, { (1<<MACH_BASE) } } }, /* FRdoublej: source register 2 */ { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[12] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, { 0, { (1<<MACH_BASE) } } }, /* FRdoublek: target register */ { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[13] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, { 0, { (1<<MACH_BASE) } } }, /* CRi: source register 1 */ { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3, - { 0, { (const PTR) &frv_cgen_ifld_table[23] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } }, { 0, { (1<<MACH_BASE) } } }, /* CRj: source register 2 */ { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3, - { 0, { (const PTR) &frv_cgen_ifld_table[24] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } }, { 0, { (1<<MACH_BASE) } } }, /* CRj_int: destination register */ { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[27] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } }, { 0, { (1<<MACH_BASE) } } }, /* CRj_float: destination register */ { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[28] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } }, { 0, { (1<<MACH_BASE) } } }, /* CRk: destination register */ { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3, - { 0, { (const PTR) &frv_cgen_ifld_table[25] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } }, { 0, { (1<<MACH_BASE) } } }, /* CCi: condition register */ { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3, - { 0, { (const PTR) &frv_cgen_ifld_table[26] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } }, { 0, { (1<<MACH_BASE) } } }, /* ICCi_1: condition register */ { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[29] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } }, { 0, { (1<<MACH_BASE) } } }, /* ICCi_2: condition register */ { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[30] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } }, { 0, { (1<<MACH_BASE) } } }, /* ICCi_3: condition register */ { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[31] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } }, { 0, { (1<<MACH_BASE) } } }, /* FCCi_1: condition register */ { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[32] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } }, { 0, { (1<<MACH_BASE) } } }, /* FCCi_2: condition register */ { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[33] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } }, { 0, { (1<<MACH_BASE) } } }, /* FCCi_3: condition register */ { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[34] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } }, { 0, { (1<<MACH_BASE) } } }, /* FCCk: condition register */ { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[35] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } }, { 0, { (1<<MACH_BASE) } } }, /* eir: exception insn reg */ { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[36] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } }, { 0, { (1<<MACH_BASE) } } }, /* s10: 10 bit signed immediate */ { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10, - { 0, { (const PTR) &frv_cgen_ifld_table[37] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* u16: 16 bit unsigned immediate */ { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16, - { 0, { (const PTR) &frv_cgen_ifld_table[40] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* s16: 16 bit signed immediate */ { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16, - { 0, { (const PTR) &frv_cgen_ifld_table[41] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* s6: 6 bit signed immediate */ { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[42] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* s6_1: 6 bit signed immediate */ { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[43] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* u6: 6 bit unsigned immediate */ { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6, - { 0, { (const PTR) &frv_cgen_ifld_table[44] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* s5: 5 bit signed immediate */ { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5, - { 0, { (const PTR) &frv_cgen_ifld_table[45] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* cond: conditional arithmetic */ { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[50] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* ccond: lr branch condition */ { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[51] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* hint: 2 bit branch predictor */ { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[52] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* hint_taken: 2 bit branch predictor */ { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[52] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, { 0, { (1<<MACH_BASE) } } }, /* hint_not_taken: 2 bit branch predictor */ { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2, - { 0, { (const PTR) &frv_cgen_ifld_table[52] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, { 0, { (1<<MACH_BASE) } } }, /* LI: link indicator */ { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[53] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } }, { 0, { (1<<MACH_BASE) } } }, /* lock: cache lock indicator */ { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[54] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* debug: debug mode indicator */ { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[55] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* A: all accumulator indicator */ { "A", FRV_OPERAND_A, HW_H_UINT, 17, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[56] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* ae: all entries indicator */ { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1, - { 0, { (const PTR) &frv_cgen_ifld_table[57] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* label16: 18 bit pc relative address */ { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16, - { 0, { (const PTR) &frv_cgen_ifld_table[60] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* label24: 26 bit pc relative address */ { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24, @@ -2172,11 +2175,11 @@ const CGEN_OPERAND frv_cgen_operand_table[] = { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, /* d12: 12 bit signed immediate */ { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12, - { 0, { (const PTR) &frv_cgen_ifld_table[39] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, { 0, { (1<<MACH_BASE) } } }, /* s12: 12 bit signed immediate */ { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12, - { 0, { (const PTR) &frv_cgen_ifld_table[39] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* u12: 12 bit signed immediate */ { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12, @@ -2188,15 +2191,15 @@ const CGEN_OPERAND frv_cgen_operand_table[] = { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, /* ulo16: 16 bit unsigned immediate, for #lo() */ { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16, - { 0, { (const PTR) &frv_cgen_ifld_table[40] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, { 0, { (1<<MACH_BASE) } } }, /* slo16: 16 bit unsigned immediate, for #lo() */ { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16, - { 0, { (const PTR) &frv_cgen_ifld_table[41] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } }, { 0, { (1<<MACH_BASE) } } }, /* uhi16: 16 bit unsigned immediate, for #hi() */ { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16, - { 0, { (const PTR) &frv_cgen_ifld_table[40] } }, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, { 0, { (1<<MACH_BASE) } } }, /* psr_esr: PSR.ESR bit */ { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0, diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h index 893919f..53cad79 100644 --- a/opcodes/frv-desc.h +++ b/opcodes/frv-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c index 9632557..5e56e35 100644 --- a/opcodes/frv-opc.c +++ b/opcodes/frv-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h index 266031b..018a643 100644 --- a/opcodes/frv-opc.h +++ b/opcodes/frv-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/ip2k-desc.c b/opcodes/ip2k-desc.c index ab6f7bf..f8e4932 100644 --- a/opcodes/ip2k-desc.c +++ b/opcodes/ip2k-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -348,39 +348,39 @@ const CGEN_OPERAND ip2k_cgen_operand_table[] = { /* pc: program counter */ { "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0, - { 0, { (const PTR) &ip2k_cgen_ifld_table[0] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_NIL] } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* addr16cjp: 13-bit address */ { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13, - { 0, { (const PTR) &ip2k_cgen_ifld_table[4] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_ADDR16CJP] } }, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, /* fr: register */ { "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9, - { 0, { (const PTR) &ip2k_cgen_ifld_table[3] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_REG] } }, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, /* lit8: 8-bit signed literal */ { "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8, - { 0, { (const PTR) &ip2k_cgen_ifld_table[2] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, { 0, { (1<<MACH_BASE) } } }, /* bitno: bit number */ { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3, - { 0, { (const PTR) &ip2k_cgen_ifld_table[6] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_BITNO] } }, { 0, { (1<<MACH_BASE) } } }, /* addr16p: page number */ { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3, - { 0, { (const PTR) &ip2k_cgen_ifld_table[16] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_PAGE3] } }, { 0, { (1<<MACH_BASE) } } }, /* addr16h: high 8 bits of address */ { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8, - { 0, { (const PTR) &ip2k_cgen_ifld_table[2] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, { 0, { (1<<MACH_BASE) } } }, /* addr16l: low 8 bits of address */ { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8, - { 0, { (const PTR) &ip2k_cgen_ifld_table[2] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_IMM8] } }, { 0, { (1<<MACH_BASE) } } }, /* reti3: reti flags */ { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3, - { 0, { (const PTR) &ip2k_cgen_ifld_table[14] } }, + { 0, { (const PTR) &ip2k_cgen_ifld_table[IP2K_F_RETI3] } }, { 0, { (1<<MACH_BASE) } } }, /* pabits: page bits */ { "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0, diff --git a/opcodes/ip2k-desc.h b/opcodes/ip2k-desc.h index 74819ac..84db7fb 100644 --- a/opcodes/ip2k-desc.h +++ b/opcodes/ip2k-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/ip2k-opc.c b/opcodes/ip2k-opc.c index 691cc78..5140cff 100644 --- a/opcodes/ip2k-opc.c +++ b/opcodes/ip2k-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/ip2k-opc.h b/opcodes/ip2k-opc.h index 2f8a2e1..041cb04 100644 --- a/opcodes/ip2k-opc.h +++ b/opcodes/ip2k-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c index 98fecb2..30a0719 100644 --- a/opcodes/m32r-desc.c +++ b/opcodes/m32r-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -320,67 +320,67 @@ const CGEN_OPERAND m32r_cgen_operand_table[] = { /* pc: program counter */ { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0, - { 0, { (const PTR) &m32r_cgen_ifld_table[0] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* sr: source register */ { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4, - { 0, { (const PTR) &m32r_cgen_ifld_table[6] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, { 0, { (1<<MACH_BASE) } } }, /* dr: destination register */ { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4, - { 0, { (const PTR) &m32r_cgen_ifld_table[5] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, { 0, { (1<<MACH_BASE) } } }, /* src1: source register 1 */ { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4, - { 0, { (const PTR) &m32r_cgen_ifld_table[5] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, { 0, { (1<<MACH_BASE) } } }, /* src2: source register 2 */ { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4, - { 0, { (const PTR) &m32r_cgen_ifld_table[6] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, { 0, { (1<<MACH_BASE) } } }, /* scr: source control register */ { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4, - { 0, { (const PTR) &m32r_cgen_ifld_table[6] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, { 0, { (1<<MACH_BASE) } } }, /* dcr: destination control register */ { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4, - { 0, { (const PTR) &m32r_cgen_ifld_table[5] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, { 0, { (1<<MACH_BASE) } } }, /* simm8: 8 bit signed immediate */ { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8, - { 0, { (const PTR) &m32r_cgen_ifld_table[7] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* simm16: 16 bit signed immediate */ { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16, - { 0, { (const PTR) &m32r_cgen_ifld_table[8] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* uimm4: 4 bit trap number */ { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4, - { 0, { (const PTR) &m32r_cgen_ifld_table[10] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* uimm5: 5 bit shift count */ { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5, - { 0, { (const PTR) &m32r_cgen_ifld_table[11] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* uimm16: 16 bit unsigned immediate */ { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16, - { 0, { (const PTR) &m32r_cgen_ifld_table[12] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, /* imm1: 1 bit immediate */ { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1, - { 0, { (const PTR) &m32r_cgen_ifld_table[25] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } }, { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } }, /* accd: accumulator destination register */ { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2, - { 0, { (const PTR) &m32r_cgen_ifld_table[22] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } }, { 0, { (1<<MACH_M32RX) } } }, /* accs: accumulator source register */ { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2, - { 0, { (const PTR) &m32r_cgen_ifld_table[21] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } }, { 0, { (1<<MACH_M32RX) } } }, /* acc: accumulator reg (d) */ { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1, - { 0, { (const PTR) &m32r_cgen_ifld_table[20] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } }, { 0, { (1<<MACH_M32RX) } } }, /* hash: # prefix */ { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0, @@ -388,31 +388,31 @@ const CGEN_OPERAND m32r_cgen_operand_table[] = { 0, { (1<<MACH_BASE) } } }, /* hi16: high 16 bit immediate, sign optional */ { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16, - { 0, { (const PTR) &m32r_cgen_ifld_table[14] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } }, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, /* slo16: 16 bit signed immediate, for low() */ { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16, - { 0, { (const PTR) &m32r_cgen_ifld_table[8] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, { 0, { (1<<MACH_BASE) } } }, /* ulo16: 16 bit unsigned immediate, for low() */ { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16, - { 0, { (const PTR) &m32r_cgen_ifld_table[12] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, { 0, { (1<<MACH_BASE) } } }, /* uimm24: 24 bit address */ { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24, - { 0, { (const PTR) &m32r_cgen_ifld_table[13] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } }, { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } }, /* disp8: 8 bit displacement */ { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8, - { 0, { (const PTR) &m32r_cgen_ifld_table[15] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } }, { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* disp16: 16 bit displacement */ { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16, - { 0, { (const PTR) &m32r_cgen_ifld_table[16] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } }, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* disp24: 24 bit displacement */ { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24, - { 0, { (const PTR) &m32r_cgen_ifld_table[17] } }, + { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } }, { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* condbit: condition bit */ { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0, diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h index b099730..85e22ee 100644 --- a/opcodes/m32r-desc.h +++ b/opcodes/m32r-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index 5b20f4d..b60c1bf 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h index 0a69dc4..22e6924 100644 --- a/opcodes/m32r-opc.h +++ b/opcodes/m32r-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c index f89c230..5365d15 100644 --- a/opcodes/m32r-opinst.c +++ b/opcodes/m32r-opinst.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c index 5ec4766..6de9107 100644 --- a/opcodes/openrisc-desc.c +++ b/opcodes/openrisc-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -242,6 +242,7 @@ const CGEN_IFLD openrisc_cgen_ifld_table[] = { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } } }, { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } } }, { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, @@ -264,8 +265,8 @@ const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] = { - { 0, { (const PTR) &openrisc_cgen_ifld_table[19] } }, - { 0, { (const PTR) &openrisc_cgen_ifld_table[20] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_1] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_2] } }, { 0, { (const PTR) 0 } } }; @@ -286,7 +287,7 @@ const CGEN_OPERAND openrisc_cgen_operand_table[] = { /* pc: program counter */ { "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0, - { 0, { (const PTR) &openrisc_cgen_ifld_table[0] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_NIL] } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* sr: special register */ { "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0, @@ -298,51 +299,51 @@ const CGEN_OPERAND openrisc_cgen_operand_table[] = { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* simm-16: 16 bit signed immediate */ { "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16, - { 0, { (const PTR) &openrisc_cgen_ifld_table[7] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, { 0, { (1<<MACH_BASE) } } }, /* uimm-16: 16 bit unsigned immediate */ { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16, - { 0, { (const PTR) &openrisc_cgen_ifld_table[8] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM16] } }, { 0, { (1<<MACH_BASE) } } }, /* disp-26: pc-rel 26 bit */ { "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26, - { 0, { (const PTR) &openrisc_cgen_ifld_table[21] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_DISP26] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* abs-26: abs 26 bit */ { "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26, - { 0, { (const PTR) &openrisc_cgen_ifld_table[22] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_ABS26] } }, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, /* uimm-5: imm5 */ { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5, - { 0, { (const PTR) &openrisc_cgen_ifld_table[9] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM5] } }, { 0, { (1<<MACH_BASE) } } }, /* rD: destination register */ { "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5, - { 0, { (const PTR) &openrisc_cgen_ifld_table[4] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R1] } }, { 0, { (1<<MACH_BASE) } } }, /* rA: source register A */ { "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5, - { 0, { (const PTR) &openrisc_cgen_ifld_table[5] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R2] } }, { 0, { (1<<MACH_BASE) } } }, /* rB: source register B */ { "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5, - { 0, { (const PTR) &openrisc_cgen_ifld_table[6] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R3] } }, { 0, { (1<<MACH_BASE) } } }, /* op-f-23: f-op23 */ { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3, - { 0, { (const PTR) &openrisc_cgen_ifld_table[15] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP4] } }, { 0, { (1<<MACH_BASE) } } }, /* op-f-3: f-op3 */ { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5, - { 0, { (const PTR) &openrisc_cgen_ifld_table[16] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP5] } }, { 0, { (1<<MACH_BASE) } } }, /* hi16: high 16 bit immediate, sign optional */ { "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16, - { 0, { (const PTR) &openrisc_cgen_ifld_table[7] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, /* lo16: low 16 bit immediate, sign optional */ { "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16, - { 0, { (const PTR) &openrisc_cgen_ifld_table[11] } }, + { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_LO16] } }, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, /* ui16nc: 16 bit immediate, sign optional */ { "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16, diff --git a/opcodes/openrisc-desc.h b/opcodes/openrisc-desc.h index a85930e..d1edee2 100644 --- a/opcodes/openrisc-desc.h +++ b/opcodes/openrisc-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c index 687996c..943f4d5 100644 --- a/opcodes/openrisc-opc.c +++ b/opcodes/openrisc-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/openrisc-opc.h b/opcodes/openrisc-opc.h index 494ba5c..bd8bb7c 100644 --- a/opcodes/openrisc-opc.h +++ b/opcodes/openrisc-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/xstormy16-desc.c b/opcodes/xstormy16-desc.c index 77d7613..9c9f30b 100644 --- a/opcodes/xstormy16-desc.c +++ b/opcodes/xstormy16-desc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -297,6 +297,7 @@ const CGEN_IFLD xstormy16_cgen_ifld_table[] = { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } }, { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } }, + { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, { 0, 0, 0, 0, 0, 0, {0, {0}} } }; @@ -313,8 +314,8 @@ const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD []; const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] = { - { 0, { (const PTR) &xstormy16_cgen_ifld_table[34] } }, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[35] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } }, { 0, { (const PTR) 0 } } }; @@ -335,7 +336,7 @@ const CGEN_OPERAND xstormy16_cgen_operand_table[] = { /* pc: program counter */ { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[0] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } }, { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* psw-z8: */ { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0, @@ -367,95 +368,95 @@ const CGEN_OPERAND xstormy16_cgen_operand_table[] = { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, /* Rd: general register destination */ { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[2] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } }, { 0, { (1<<MACH_BASE) } } }, /* Rdm: general register destination */ { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[3] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } }, { 0, { (1<<MACH_BASE) } } }, /* Rm: general register for memory */ { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[4] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } }, { 0, { (1<<MACH_BASE) } } }, /* Rs: general register source */ { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[5] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } }, { 0, { (1<<MACH_BASE) } } }, /* Rb: base register */ { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[6] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } }, { 0, { (1<<MACH_BASE) } } }, /* Rbj: base register for jump */ { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[7] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } }, { 0, { (1<<MACH_BASE) } } }, /* bcond2: branch condition opcode */ { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[9] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } }, { 0, { (1<<MACH_BASE) } } }, /* ws2: word size opcode */ { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[11] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } }, { 0, { (1<<MACH_BASE) } } }, /* bcond5: branch condition opcode */ { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[18] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } }, { 0, { (1<<MACH_BASE) } } }, /* imm2: 2 bit unsigned immediate */ { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[21] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } }, { 0, { (1<<MACH_BASE) } } }, /* imm3: 3 bit unsigned immediate */ { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[22] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } }, { 0, { (1<<MACH_BASE) } } }, /* imm3b: 3 bit unsigned immediate for bit tests */ { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[23] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } }, { 0, { (1<<MACH_BASE) } } }, /* imm4: 4 bit unsigned immediate */ { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[24] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } }, { 0, { (1<<MACH_BASE) } } }, /* imm8: 8 bit unsigned immediate */ { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[25] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, { 0, { (1<<MACH_BASE) } } }, /* imm8small: 8 bit unsigned immediate */ { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[25] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, { 0, { (1<<MACH_BASE) } } }, /* imm12: 12 bit signed immediate */ { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[26] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } }, { 0, { (1<<MACH_BASE) } } }, /* imm16: 16 bit immediate */ { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[27] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } }, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, /* lmem8: 8 bit unsigned immediate low memory */ { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[28] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } }, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, /* hmem8: 8 bit unsigned immediate high memory */ { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[29] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } }, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, /* rel8-2: 8 bit relative address */ { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[30] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* rel8-4: 8 bit relative address */ { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[31] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* rel12: 12 bit relative address */ { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[32] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* rel12a: 12 bit relative address */ { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11, - { 0, { (const PTR) &xstormy16_cgen_ifld_table[33] } }, + { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } }, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, /* abs24: 24 bit absolute address */ { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24, @@ -1118,6 +1119,11 @@ static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] = XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16, { 0, { (1<<MACH_BASE) } } }, +/* reset */ + { + XSTORMY16_INSN_RESET, "reset", "reset", 16, + { 0, { (1<<MACH_BASE) } } + }, /* nop */ { XSTORMY16_INSN_NOP, "nop", "nop", 16, diff --git a/opcodes/xstormy16-desc.h b/opcodes/xstormy16-desc.h index fe18a13..a880321 100644 --- a/opcodes/xstormy16-desc.h +++ b/opcodes/xstormy16-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. diff --git a/opcodes/xstormy16-opc.c b/opcodes/xstormy16-opc.c index 90db6f0..34c0b0e 100644 --- a/opcodes/xstormy16-opc.c +++ b/opcodes/xstormy16-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -910,6 +910,12 @@ static const CGEN_OPCODE xstormy16_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, 0 } }, & ifmt_iret, { 0xe0 } }, +/* reset */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_iret, { 0xf } + }, /* nop */ { { 0, 0, 0, 0 }, diff --git a/opcodes/xstormy16-opc.h b/opcodes/xstormy16-opc.h index fbe7fe1..f2366ca 100644 --- a/opcodes/xstormy16-opc.h +++ b/opcodes/xstormy16-opc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -67,8 +67,9 @@ typedef enum cgen_insn_type { , XSTORMY16_INSN_CALLRGR, XSTORMY16_INSN_CALLRIMM, XSTORMY16_INSN_CALLGR, XSTORMY16_INSN_CALLFIMM , XSTORMY16_INSN_ICALLRGR, XSTORMY16_INSN_ICALLGR, XSTORMY16_INSN_ICALLFIMM, XSTORMY16_INSN_IRET , XSTORMY16_INSN_RET, XSTORMY16_INSN_MUL, XSTORMY16_INSN_DIV, XSTORMY16_INSN_SDIV - , XSTORMY16_INSN_SDIVLH, XSTORMY16_INSN_DIVLH, XSTORMY16_INSN_NOP, XSTORMY16_INSN_HALT - , XSTORMY16_INSN_HOLD, XSTORMY16_INSN_HOLDX, XSTORMY16_INSN_BRK, XSTORMY16_INSN_SYSCALL + , XSTORMY16_INSN_SDIVLH, XSTORMY16_INSN_DIVLH, XSTORMY16_INSN_RESET, XSTORMY16_INSN_NOP + , XSTORMY16_INSN_HALT, XSTORMY16_INSN_HOLD, XSTORMY16_INSN_HOLDX, XSTORMY16_INSN_BRK + , XSTORMY16_INSN_SYSCALL } CGEN_INSN_TYPE; /* Index of `invalid' insn place holder. */ |