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author | Jan Beulich <jbeulich@suse.com> | 2022-10-18 08:27:42 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2022-10-18 08:27:42 +0200 |
commit | 32e876a80f015281cd7fca46e8a589c6cf132d11 (patch) | |
tree | cdb71d54f8216314f83e44f6d0f874ae14d89f99 | |
parent | f117661d3ca39b36ba4e7673e422e89e7e9afb85 (diff) | |
download | binutils-32e876a80f015281cd7fca46e8a589c6cf132d11.zip binutils-32e876a80f015281cd7fca46e8a589c6cf132d11.tar.gz binutils-32e876a80f015281cd7fca46e8a589c6cf132d11.tar.bz2 |
x86: generalize gas documentation for disabling of ISA extensions
As of commit ae89daecb132 ("x86: generalize disabling of sub-
architectures") there's no arbitrary subset of ISAs which can also be
disabled. This should have been reflected in documentation right away.
Since I failed to do so, correct this now.
-rw-r--r-- | gas/doc/c-i386.texi | 54 |
1 files changed, 5 insertions, 49 deletions
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index c4a3967..d4f5018 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -137,16 +137,9 @@ accept various extension mnemonics. For example, @code{287}, @code{387}, @code{687}, -@code{no87}, -@code{no287}, -@code{no387}, -@code{no687}, @code{cmov}, -@code{nocmov}, @code{fxsr}, -@code{nofxsr}, @code{mmx}, -@code{nommx}, @code{sse}, @code{sse2}, @code{sse3}, @@ -155,18 +148,8 @@ accept various extension mnemonics. For example, @code{sse4.1}, @code{sse4.2}, @code{sse4}, -@code{nosse}, -@code{nosse2}, -@code{nosse3}, -@code{nosse4a}, -@code{nossse3}, -@code{nosse4.1}, -@code{nosse4.2}, -@code{nosse4}, @code{avx}, @code{avx2}, -@code{noavx}, -@code{noavx2}, @code{adx}, @code{rdseed}, @code{prfchw}, @@ -189,9 +172,7 @@ accept various extension mnemonics. For example, @code{serialize}, @code{tsxldtrk}, @code{kl}, -@code{nokl}, @code{widekl}, -@code{nowidekl}, @code{hreset}, @code{avx512f}, @code{avx512cd}, @@ -213,37 +194,9 @@ accept various extension mnemonics. For example, @code{avx512_bf16}, @code{avx_vnni}, @code{avx512_fp16}, -@code{noavx512f}, -@code{noavx512cd}, -@code{noavx512er}, -@code{noavx512pf}, -@code{noavx512vl}, -@code{noavx512bw}, -@code{noavx512dq}, -@code{noavx512ifma}, -@code{noavx512vbmi}, -@code{noavx512_4fmaps}, -@code{noavx512_4vnniw}, -@code{noavx512_vpopcntdq}, -@code{noavx512_vbmi2}, -@code{noavx512_vnni}, -@code{noavx512_bitalg}, -@code{noavx512_vp2intersect}, -@code{notdx}, -@code{noavx512_bf16}, -@code{noavx_vnni}, -@code{noavx512_fp16}, -@code{noenqcmd}, -@code{noserialize}, -@code{notsxldtrk}, @code{amx_int8}, -@code{noamx_int8}, @code{amx_bf16}, -@code{noamx_bf16}, @code{amx_tile}, -@code{noamx_tile}, -@code{nouintr}, -@code{nohreset}, @code{vmx}, @code{vmfunc}, @code{smx}, @@ -291,8 +244,8 @@ accept various extension mnemonics. For example, @code{tlbsync}, @code{svme} and @code{padlock}. -Note that rather than extending a basic instruction set, the extension -mnemonics starting with @code{no} revoke the respective functionality. +Note that these extension mnemonics can be prefixed with @code{no} to revoke +the respective (and any dependent) functionality. When the @code{.arch} directive is used with @option{-march}, the @code{.arch} directive will take precedent. @@ -1559,6 +1512,9 @@ conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target. +Note that the sub-architecture specifiers (starting with a dot) can be prefixed +with @code{no} to revoke the respective (and any dependent) functionality. + Following the CPU architecture (but not a sub-architecture, which are those starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to control automatic promotion of conditional jumps. @samp{jumps} is the |