CSKY: Add FPUV3 instructions, which supported by ck860f.

Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com> gas/ * config/tc-csky.c (float_work_fpuv3_fmovi): New function, helper function to encode fpuv3 fmovi instructions. (float_work_fpuv3_fstore): New function. (struct literal): Add new member 'offset'. (csky_cpus): New cpu CK860f. (enter_literal): Return literal pool pointer instead of offset. (parse_rt): Adjust the change of enter_literal. (parse_rtf): Likewise. (v1_work_lrw): Likewise. (v1_work_jbsr): Likewise. (v2_work_lrw): Likewise. (v2_work_jbsr): Likewise. (v2_work_jsri): Likewise. (vdsp_work_vlrw): Likewise. (is_freglist_legal): Add handler for FPUV3. (parse_type_freg): Likewise. (is_imm_within_range): Set e.X_add_number if it is a signed and negtive number. (get_operand_value): Add handler for OPRND_TYPE_IMM9b, OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. (float_to_half): Convert float number to harf float. opcodes/ * csky-dis.c (csky_output_operand): Add handlers for OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH to support FPUV3 instructions. * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b, OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8, OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24, OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22, OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25, OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25, OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21, OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24, OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25, OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20, OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25, OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24, OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20, OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define. (csky_v2_opcodes): Add FPUV3 instructions. include/ * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.
author: Cooper Qu <cooper.qu@linux.alibaba.com> 2020-09-07 17:24:11 +0800
committer: Lifang Xia <lifang_xia@c-sky.com> 2020-09-09 19:25:40 +0800
commit: 1feede9b384ef80a268ffe0b18e75bd60574f7c7 (patch)
tree: 2981852750a2405cc1cdf1cfade31ca5d7574ba0
parent: dfbee68088e822453fdc82f6b8a3a5bc468944b1 (diff)
download: binutils-1feede9b384ef80a268ffe0b18e75bd60574f7c7.zip
binutils-1feede9b384ef80a268ffe0b18e75bd60574f7c7.tar.gz
binutils-1feede9b384ef80a268ffe0b18e75bd60574f7c7.tar.bz2
7 files changed, 2356 insertions, 33 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7335e83..a4757cc 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,31 @@
+2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+	* config/tc-csky.c (float_work_fpuv3_fmovi): New function,
+	helper function to encode fpuv3 fmovi instructions.
+	(float_work_fpuv3_fstore): New function.
+	(struct literal): Add new member 'offset'.
+	(csky_cpus): New cpu CK860f.
+	(enter_literal): Return literal pool pointer instead of offset.
+	(parse_rt): Adjust the change of enter_literal.
+	(parse_rtf): Likewise.
+	(v1_work_lrw): Likewise.
+	(v1_work_jbsr): Likewise.
+	(v2_work_lrw): Likewise.
+	(v2_work_jbsr): Likewise.
+	(v2_work_jsri): Likewise.
+	(vdsp_work_vlrw): Likewise.
+	(is_freglist_legal): Add handler for FPUV3.
+	(parse_type_freg): Likewise.
+	(is_imm_within_range): Set e.X_add_number if it is a signed and
+	negtive number.
+	(get_operand_value): Add handler for OPRND_TYPE_IMM9b,
+	OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI
+	and OPRND_TYPE_DFLOAT_FMOVI.
+	(float_to_half): Convert float number to harf float.
+	* testsuite/gas/csky/case-fpuv3-ck860f/ : New folder containing
+	the test cases for FPUV3, they are divided by instruction
+	operands format and both have legal cases and illegal cases.
+
 2020-09-08  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
 	Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 
diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c
index 0ed39e4..1415545 100644
--- a/gas/config/tc-csky.c
+++ b/gas/config/tc-csky.c
@@ -172,6 +172,8 @@ bfd_boolean v2_work_movih (void);
 bfd_boolean v2_work_ori (void);
 bfd_boolean float_work_fmovi (void);
 bfd_boolean dsp_work_bloop (void);
+bfd_boolean float_work_fpuv3_fmovi (void);
+bfd_boolean float_work_fpuv3_fstore (void);
 
 /* csky-opc.h must be included after workers are declared.  */
 #include "opcodes/csky-opc.h"
@@ -295,6 +297,7 @@ struct csky_insn_info
 struct literal
 {
   unsigned short  refcnt;
+  unsigned int    offset;
   unsigned char   ispcrel;
   unsigned char   unused;
   bfd_reloc_code_real_type r_type;
@@ -704,9 +707,10 @@ const struct csky_cpu_info csky_cpus[] =
   {"ck810ftv", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST},
 
   /* CK860 Series.  */
-#define CSKY_ISA_860    (CSKY_ISA_810 | CSKYV2_ISA_10E60)
-#define CSKY_ISA_FLOAT_860 (CSKY_ISA_FLOAT_810)
+#define CSKY_ISA_860    (CSKY_ISA_810 | CSKYV2_ISA_10E60 | CSKYV2_ISA_3E3R3)
+#define CSKY_ISA_860F (CSKY_ISA_860 | CSKY_ISA_FLOAT_7E60)
   {"ck860", CSKY_ARCH_860, CSKY_ISA_860},
+  {"ck860f", CSKY_ARCH_860, CSKY_ISA_860F},
 
   {NULL, 0, 0}
 };
@@ -1718,7 +1722,7 @@ dump_literals (int isforce)
   poolsize = 0;
 }
 
-static int
+static struct literal *
 enter_literal (expressionS *e,
 	       int ispcrel,
 	       unsigned char isdouble,
@@ -1772,7 +1776,7 @@ enter_literal (expressionS *e,
 			  p->e.X_add_number * sizeof (LITTLENUM_TYPE)) == 0)))
 	{
 	  p->refcnt ++;
-	  return i;
+	  return p;
 	}
       if (p->e.X_op == O_big)
 	{
@@ -1787,6 +1791,7 @@ enter_literal (expressionS *e,
   p->e = *e;
   p->r_type = insn_reloc;
   p->isdouble = isdouble;
+  p->offset = i;
   if (isdouble)
     p->dbnum = dbnum;
   if (e->X_op == O_big)
@@ -1806,7 +1811,7 @@ enter_literal (expressionS *e,
   } else
   poolsize += (p->isdouble ? 2 : 1);
 
-  return i;
+  return p;
 }
 
 /* Check whether we must dump the literal pool here.
@@ -2056,7 +2061,6 @@ parse_rt (char *s,
 	  long reg ATTRIBUTE_UNUSED)
 {
   expressionS e;
-  int n;
 
   if (ep)
     /* Indicate nothing there.  */
@@ -2089,24 +2093,45 @@ parse_rt (char *s,
       /* If the instruction has work, literal handling is in the work.  */
       if (!csky_insn.opcode->work)
 	{
-	  n = enter_literal (&e, ispcrel, 0, 0);
+	  struct literal *p = enter_literal (&e, ispcrel, 0, 0);
 	  if (ep)
 	   *ep = e;
 
 	  /* Create a reference to pool entry.  */
 	  ep->X_op = O_symbol;
 	  ep->X_add_symbol = poolsym;
-	  ep->X_add_number = n << 2;
+	  ep->X_add_number = p->offset << 2;
 	}
     }
   return s;
 }
 
+static int float_to_half (void *f, void *h)
+{
+  int imm_e;
+  int imm_f;
+  unsigned int value_f = *(unsigned int *)f;
+  unsigned short value_h;
+
+  imm_e = ((value_f >> 23) & 0xff);
+  imm_f = ((value_f  & 0x7fffff));
+
+  imm_e = ((imm_e - 127 + 15) << 10);
+  imm_f = ((imm_f & 0x7fe000) >> 13);
+
+  value_h = (value_f & 0x80000000 ? 0x8000 : 0x0) | imm_e | imm_f;
+
+  if (h)
+    *(unsigned short *)h = value_h;
+
+  return value_h;
+}
+
 static char *
 parse_rtf (char *s, int ispcrel, expressionS *ep)
 {
   expressionS e;
-  int n = 0;
+  struct literal *p = NULL;
 
   if (ep)
     /* Indicate nothing there.  */
@@ -2127,15 +2152,24 @@ parse_rtf (char *s, int ispcrel, expressionS *ep)
   else
     {
       uint64_t dbnum;
-      if (strstr (csky_insn.opcode->mnemonic, "flrws"))
+      if (strstr(csky_insn.opcode->mnemonic, "flrws")
+	  || strstr(csky_insn.opcode->mnemonic, "flrw.32"))
 	{
 	  s = parse_fexp (s, &e, 0, &dbnum);
-	  n = enter_literal (&e, ispcrel, 0, dbnum);
+	  p = enter_literal (& e, ispcrel, 0, dbnum);
 	}
-      else if (strstr (csky_insn.opcode->mnemonic, "flrwd"))
+      else if (strstr(csky_insn.opcode->mnemonic, "flrwd")
+	       || strstr(csky_insn.opcode->mnemonic, "flrw.64"))
 	{
 	  s = parse_fexp (s, &e, 1, &dbnum);
-	  n = enter_literal (&e, ispcrel, 1, dbnum);
+	  p = enter_literal (& e, ispcrel, 1, dbnum);
+	}
+      else if (strstr(csky_insn.opcode->mnemonic, "flrwh")
+	       || strstr(csky_insn.opcode->mnemonic, "flrw.16"))
+	{
+	  s = parse_fexp (s, &e, 0, NULL);
+	  e.X_add_number = float_to_half (&e.X_add_number, &e.X_add_number);
+	  p = enter_literal (& e, ispcrel, 0, 0);
 	}
       else
 	as_bad (_("unrecognized opcode"));
@@ -2146,7 +2180,7 @@ parse_rtf (char *s, int ispcrel, expressionS *ep)
       /* Create a reference to pool entry.  */
       ep->X_op         = O_symbol;
       ep->X_add_symbol = poolsym;
-      ep->X_add_number = n << 2;
+      ep->X_add_number = p->offset << 2;
     }
   return s;
 }
@@ -2592,6 +2626,7 @@ is_freglist_legal (char **oper)
   int reg1 = -1;
   int reg2 = -1;
   int len = 0;
+  int shift = 0;
   reg1 = csky_get_freg_val  (*oper, &len);
   *oper += len;
 
@@ -2627,12 +2662,34 @@ is_freglist_legal (char **oper)
     }
 
   reg2 = reg2 - reg1;
-  if (reg2 > (int)0x3)
+  /* The fldm/fstm in CSKY_ISA_FLOAT_7E60 has 5 bits frz(reg1).  */
+  shift = 4;
+  if (strncmp (csky_insn.opcode->mnemonic, "fstm", 4) == 0
+      || strncmp (csky_insn.opcode->mnemonic, "fldm", 4) == 0)
+    {
+      if ((!(isa_flag & CSKY_ISA_FLOAT_7E60)
+	   && (reg2 > (int)15 || reg1 > 15))
+	  || ((isa_flag & CSKY_ISA_FLOAT_7E60)
+	      && (reg2 > (int)31 || reg1 > (int)31)))
+	{
+	  /* ISA_FLOAT_E1 fstm/fldm fry-frx is within 15.
+	     ISA_FLOAT_7E60 fstm(u)/fldm(u) frx-fry is within 31.  */
+	  SET_ERROR_STRING(ERROR_REG_FORMAT, (void *)"frx-fry is over range");
+	  return FALSE;
+	}
+      if ((mach_flag & CSKY_ARCH_MASK) == CSKY_ARCH_860)
+	{
+	  shift = 5;
+	}
+    }
+  else
     {
-      SET_ERROR_STRING(ERROR_REG_FORMAT, (void *)"vry-vrx is over range");
-      return FALSE;
+      if (reg2 > (int)0x3) {
+        SET_ERROR_STRING(ERROR_REG_FORMAT, (void *)"vry-vrx is over range");
+        return FALSE;
+      }
     }
-  reg2 <<= 4;
+  reg2 <<= shift;
   reg1 |= reg2;
   csky_insn.val[csky_insn.idx++] = reg1;
   return TRUE;
@@ -2788,6 +2845,8 @@ is_imm_within_range (char **oper, int min, int max)
 	  ret = FALSE;
 	  SET_ERROR_STRING (ERROR_IMM_OVERFLOW, NULL);
 	}
+      if (!e.X_unsigned)
+	e.X_add_number |= 0x80000000;
       csky_insn.val[csky_insn.idx++] = e.X_add_number;
     }
 
@@ -2990,7 +3049,8 @@ parse_type_freg (char** oper, int even)
     }
 
   if (IS_CSKY_V2 (mach_flag)
-      && (csky_insn.opcode->isa_flag32 & CSKY_ISA_VDSP_2)
+      && ((csky_insn.opcode->isa_flag32 & CSKY_ISA_VDSP_2)
+	  || !(csky_insn.opcode->isa_flag32 & CSKY_ISA_FLOAT_7E60))
       && reg > 15)
     {
       if ((csky_insn.opcode->isa_flag32 & CSKY_ISA_VDSP_2))
@@ -3537,6 +3597,8 @@ get_operand_value (struct csky_opcode_info *op,
       return is_imm_within_range (oper, 0, 127);
     case OPRND_TYPE_IMM8b:
       return is_imm_within_range (oper, 0, 255);
+    case OPRND_TYPE_IMM9b:
+      return is_imm_within_range (oper, -256, 255);
     case OPRND_TYPE_IMM12b:
       return is_imm_within_range (oper, 0, 4095);
     case OPRND_TYPE_IMM15b:
@@ -3720,7 +3782,37 @@ get_operand_value (struct csky_opcode_info *op,
 	     | ((dbnum & 0x8000000000000000ULL) >> 43));
 	return TRUE;
       }
+    case OPRND_TYPE_HFLOAT_FMOVI:
+    case OPRND_TYPE_SFLOAT_FMOVI:
+    case OPRND_TYPE_DFLOAT_FMOVI:
+      /* For fpuv3 fmovis and fmovid, which accept a constant
+	 float with a limited range.  */
+      {
+	uint64_t dbnum;
+	int imm4, imm8, sign;
+
+	*oper = parse_fexp (*oper, &csky_insn.e1, 1, &dbnum);
+	if (csky_insn.e1.X_op == O_absent)
+	  return FALSE;
 
+	/* Convert the representation from IEEE double to the 13-bit
+	   encoding used internally for fmovis and fmovid.  */
+	imm4 = 11 - (((dbnum & 0x7ff0000000000000ULL) >> 52) - 1023);
+	/* Check float range.  */
+	if ((dbnum & 0x00000fffffffffffULL) || imm4 < 0 || imm4 > 15)
+	  {
+	    csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL);
+	    return TRUE;
+	  }
+	imm8 = (dbnum & 0x000ff00000000000ULL) >> 44;
+	sign = (dbnum & 0x8000000000000000ULL) >> 58;
+	csky_insn.e1.X_add_number
+	  = (((imm8 & 0x3) << 8)
+	     | ((imm8 & 0xfc) << 18)
+	     | ((imm4 & 0xf) << 16)
+	     | sign);
+	return TRUE;
+      }
       /* For grs v2.  */
     case OPRND_TYPE_IMM_OFF18b:
       *oper = parse_exp (*oper, &csky_insn.e1);
@@ -5999,12 +6091,12 @@ v1_work_lrw (void)
       csky_insn.inst |= reg << 8;
       if (output_literal)
 	{
-	  int n = enter_literal (&csky_insn.e1, 0, 0, 0);
+	  struct literal *p = enter_literal (&csky_insn.e1, 0, 0, 0);
 
 	  /* Create a reference to pool entry.  */
 	  csky_insn.e1.X_op = O_symbol;
 	  csky_insn.e1.X_add_symbol = poolsym;
-	  csky_insn.e1.X_add_number = n << 2;
+	  csky_insn.e1.X_add_number = p->offset << 2;
 	}
 
       if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32
@@ -6212,12 +6304,12 @@ v1_work_jbsr (void)
       csky_insn.opcode_idx = 0;
       csky_insn.isize = 2;
 
-      int n = enter_literal (&csky_insn.e1, 1, 0, 0);
+      struct literal *p = enter_literal (&csky_insn.e1, 1, 0, 0);
 
       /* Create a reference to pool entry.  */
       csky_insn.e1.X_op = O_symbol;
       csky_insn.e1.X_add_symbol = poolsym;
-      csky_insn.e1.X_add_number = n << 2;
+      csky_insn.e1.X_add_number = p->offset << 2;
 
       /* Generate fixup BFD_RELOC_CKCORE_PCREL_IMM8BY4.  */
       fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal,
@@ -6226,7 +6318,7 @@ v1_work_jbsr (void)
       if (csky_insn.e1.X_op != O_absent && do_jsri2bsr)
 	/* Generate fixup BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2.  */
 	fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal,
-		     2, & (litpool + (csky_insn.e1.X_add_number >> 2))->e,
+		     2, &p->e,
 		     1, BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2);
     }
   csky_generate_insn ();
@@ -6815,11 +6907,11 @@ v2_work_lrw (void)
 
   if (output_literal)
     {
-      int n = enter_literal (&csky_insn.e1, 0, 0, 0);
+      struct literal *p = enter_literal (&csky_insn.e1, 0, 0, 0);
       /* Create a reference to pool entry.  */
       csky_insn.e1.X_op = O_symbol;
       csky_insn.e1.X_add_symbol = poolsym;
-      csky_insn.e1.X_add_number = n << 2;
+      csky_insn.e1.X_add_number = p->offset << 2;
     }
   /* If 16bit force.  */
   if (csky_insn.flag_force == INSN_OPCODE16F)
@@ -6960,11 +7052,11 @@ v2_work_jbsr (void)
     }
   else
     {
-      int n = enter_literal (&csky_insn.e1, 0, 0, 0);
+      struct literal *p = enter_literal (&csky_insn.e1, 0, 0, 0);
       csky_insn.output = frag_more (4);
       csky_insn.e1.X_op = O_symbol;
       csky_insn.e1.X_add_symbol = poolsym;
-      csky_insn.e1.X_add_number = n << 2;
+      csky_insn.e1.X_add_number = p->offset << 2;
       fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal,
 		 4, &csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM16BY4);
       if (do_jsri2bsr || IS_CSKY_ARCH_810 (mach_flag))
@@ -6994,10 +7086,10 @@ bfd_boolean
 v2_work_jsri (void)
 {
   /* dump literal.  */
-  int n = enter_literal (&csky_insn.e1, 1, 0, 0);
+  struct literal *p = enter_literal (&csky_insn.e1, 1, 0, 0);
   csky_insn.e1.X_op = O_symbol;
   csky_insn.e1.X_add_symbol = poolsym;
-  csky_insn.e1.X_add_number = n << 2;
+  csky_insn.e1.X_add_number = p->offset << 2;
 
   /* Generate relax or reloc if necessary.  */
   csky_generate_frags ();
@@ -7012,7 +7104,7 @@ v2_work_jsri (void)
 	 For 'jbsr .L1', this reloc type's symbol
 	 is bound to '.L1', isn't bound to literal pool.  */
       fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal,
-		   4, &(litpool + (csky_insn.e1.X_add_number >> 2))->e, 1,
+		   4, &p->e, 1,
 		   BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2);
       csky_insn.output = frag_more (4);
       dwarf2_emit_insn (0);
@@ -7155,6 +7247,57 @@ float_work_fmovi (void)
   return TRUE;
 }
 
+/* Like float_work_fmovi, but for FPUV3 fmovi.16, fmovi.32 and fmovi.64
+   instructions.  */
+
+bfd_boolean
+float_work_fpuv3_fmovi (void)
+{
+  int rx = csky_insn.val[0];
+  int idx = csky_insn.opcode_idx;
+  int imm4 = 0;
+  int imm8 = 0;
+  int sign = 0;
+
+  csky_insn.inst = csky_insn.opcode->op32[idx].opcode | rx;
+
+  if (csky_insn.opcode->op32[idx].operand_num == 3)
+    {
+      /* fmovi.xx frz, imm9, imm4.  */
+      imm8 = csky_insn.val[1];
+      imm4 = csky_insn.val[2];
+      if (imm8 < 0 || (imm8 & 0x80000000))
+	{
+	  sign = (1 << 5);
+	  imm8 = 0 - imm8;
+	}
+
+      if (imm8 > 255)
+	{
+	  csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL);
+	  return FALSE;
+	}
+
+      /* imm8 store at bit [25:20] and [9:8].  */
+      /* imm4 store at bit [19:16].  */
+      /* sign store at bit [5].  */
+      csky_insn.inst = csky_insn.inst
+	| ((imm8 & 0x3) << 8)
+	| ((imm8 & 0xfc) << 18)
+	| ((imm4 & 0xf) << 16)
+	| sign;
+    }
+  else
+    {
+       csky_insn.inst |= (uint32_t) csky_insn.e1.X_add_number;
+    }
+
+  csky_insn.output = frag_more(4);
+  csky_insn.isize = 4;
+  csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize);
+  return TRUE;
+}
+
 bfd_boolean
 dsp_work_bloop (void)
 {
@@ -7196,6 +7339,21 @@ dsp_work_bloop (void)
   return TRUE;
 }
 
+bfd_boolean
+float_work_fpuv3_fstore(void)
+{
+  /* Generate relax or reloc if necessary.  */
+  csky_generate_frags ();
+  /* Generate the insn by mask.  */
+  csky_generate_insn ();
+  /* Write inst to frag.  */
+  csky_write_insn (csky_insn.output,
+                   csky_insn.inst,
+                   csky_insn.isize);
+
+
+  return TRUE;
+}
 
 /* The following are for assembler directive handling.  */
 
diff --git a/include/ChangeLog b/include/ChangeLog
index 6017c8b..33998eb 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+	* opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.
+
 2020-09-08  Jozef Lawrynowicz  <jozef.l@mittosystems.com>
 	Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 
diff --git a/include/opcode/csky.h b/include/opcode/csky.h
index ab2b210..1ad7f58 100644
--- a/include/opcode/csky.h
+++ b/include/opcode/csky.h
@@ -56,6 +56,8 @@
 #define CSKY_ISA_FLOAT_1E3  (1L << 27)
 /* 807 support (803f & 807f).  */
 #define CSKY_ISA_FLOAT_3E4  (1L << 28)
+/* 860 support.  */
+#define CSKY_ISA_FLOAT_7E60 (1L << 36)
 /* Vector DSP support.  */
 #define CSKY_ISA_VDSP       (1L << 29)
 #define CSKY_ISA_VDSP_2     (1L << 30)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index adef90c..4f416bf 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,27 @@
+2020-09-07  Cooper Qu  <cooper.qu@linux.alibaba.com>
+
+	* csky-dis.c (csky_output_operand): Add handlers for
+	OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
+	OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
+	to support FPUV3 instructions.
+	* csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
+	OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
+	OPRND_TYPE_DFLOAT_FMOVI.
+	(OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
+	 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
+	 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
+	 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
+	 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
+	 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
+	 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
+	 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
+	 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
+	 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
+	 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
+	 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
+	 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
+	(csky_v2_opcodes): Add FPUV3 instructions.
+
 2020-09-08  Alex Coplan  <alex.coplan@arm.com>
 
 	* aarch64-dis.c (print_operands): Pass CPU features to
diff --git a/opcodes/csky-dis.c b/opcodes/csky-dis.c
index f815679..89f1c6b 100644
--- a/opcodes/csky-dis.c
+++ b/opcodes/csky-dis.c
@@ -623,6 +623,62 @@ csky_output_operand (char *str, struct operand const *oprnd,
 	strcat (str, buf);
 	break;
       }
+    case OPRND_TYPE_HFLOAT_FMOVI:
+    case OPRND_TYPE_SFLOAT_FMOVI:
+      {
+	int imm4;
+	int imm8;
+	imm4 = ((inst >> 16) & 0xf);
+	imm4 = (138 - imm4) << 23;
+
+	imm8 = ((inst >> 8) & 0x3);
+	imm8 |= (((inst >> 20) & 0x3f) << 2);
+	imm8 <<= 15;
+
+	value = ((inst >> 5) & 1) << 31;
+	value |= imm4 | imm8;
+
+	imm4 = 138 - (imm4 >> 23);
+	imm8 >>= 15;
+	if ((inst >> 5) & 1)
+	  {
+	    imm8 = 0 - imm8;
+	  }
+
+	float f = 0;
+	memcpy (&f, &value, sizeof (float));
+	sprintf (str, "%s%f\t// imm9:%4d, imm4:%2d", str, f, imm8, imm4);
+
+	break;
+      }
+
+    case OPRND_TYPE_DFLOAT_FMOVI:
+      {
+	uint64_t imm4;
+	uint64_t imm8;
+	uint64_t dvalue;
+	imm4 = ((inst >> 16) & 0xf);
+	imm4 = (1034 - imm4) << 52;
+
+	imm8 = ((inst >> 8) & 0x3);
+	imm8 |= (((inst >> 20) & 0x3f) << 2);
+	imm8 <<= 44;
+
+	dvalue = (((uint64_t)inst >> 5) & 1) << 63;
+	dvalue |= imm4 | imm8;
+
+	imm4 = 1034 - (imm4 >> 52);
+	imm8 >>= 44;
+	if (inst >> 5)
+	  {
+	    imm8 = 0 - imm8;
+	  }
+	double d = 0;
+	memcpy (&d, &dvalue, sizeof (double));
+	sprintf (str, "%s%lf\t// imm9:%4ld, imm4:%2ld", str, d, imm8, imm4);
+
+	break;
+      }
     case OPRND_TYPE_LABEL_WITH_BRACKET:
       sprintf (buf, "[0x%x]", (unsigned int)value);
       strcat (str, buf);
@@ -653,8 +709,20 @@ csky_output_operand (char *str, struct operand const *oprnd,
     case OPRND_TYPE_FREGLIST_DASH:
       if (IS_CSKY_V2 (mach_flag))
 	{
-	  int vrx = value & 0xf;
-	  int vry = vrx + (value >> 4);
+	  int vrx = 0;
+	  int vry = 0;
+	  if (dis_info.isa & CSKY_ISA_FLOAT_7E60
+	      && (strstr (str, "fstm") != NULL
+		  || strstr (str, "fldm") != NULL))
+	    {
+	      vrx = value & 0x1f;
+	      vry = vrx + (value >> 5);
+	    }
+	  else
+	    {
+	      vrx = value & 0xf;
+	      vry = vrx + (value >> 4);
+	    }
 	  sprintf (buf, "fr%d-fr%d", vrx, vry);
 	  strcat (str, buf);
 	}
diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 5e2f1a5..fac30ae 100644
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -116,6 +116,7 @@ enum operand_type
   OPRND_TYPE_IMM5b,
   OPRND_TYPE_IMM7b,
   OPRND_TYPE_IMM8b,
+  OPRND_TYPE_IMM9b,
   OPRND_TYPE_IMM12b,
   OPRND_TYPE_IMM15b,
   OPRND_TYPE_IMM16b,
@@ -195,6 +196,9 @@ enum operand_type
   /* Single float and double float.  */
   OPRND_TYPE_SFLOAT,
   OPRND_TYPE_DFLOAT,
+  OPRND_TYPE_HFLOAT_FMOVI,
+  OPRND_TYPE_SFLOAT_FMOVI,
+  OPRND_TYPE_DFLOAT_FMOVI,
 };
 
 /* Operand descriptors.  */
@@ -331,6 +335,7 @@ struct csky_opcode
 #define OPRND_MASK_2_5              0x3c
 #define OPRND_MASK_3_7              0xf8
 #define OPRND_MASK_4                0x10
+#define OPRND_MASK_4_5              0x30
 #define OPRND_MASK_4_6              0x70
 #define OPRND_MASK_4_7              0xf0
 #define OPRND_MASK_4_8              0x1f0
@@ -340,8 +345,13 @@ struct csky_opcode
 #define OPRND_MASK_5_7              0xe0
 #define OPRND_MASK_5_8              0x1e0
 #define OPRND_MASK_5_9              0x3e0
+#define OPRND_MASK_6                0x40
+#define OPRND_MASK_6_7              0xc0
+#define OPRND_MASK_6_8              0x1c0
 #define OPRND_MASK_6_9              0x3c0
 #define OPRND_MASK_6_10             0x7c0
+#define OPRND_MASK_7                0x80
+#define OPRND_MASK_7_8              0x180
 #define OPRND_MASK_8_9              0x300
 #define OPRND_MASK_8_10             0x700
 #define OPRND_MASK_8_11             0xf00
@@ -354,17 +364,33 @@ struct csky_opcode
 #define OPRND_MASK_16_19            0xf0000
 #define OPRND_MASK_16_20            0x1f0000
 #define OPRND_MASK_16_25            0x3ff0000
+#define OPRND_MASK_17_24            0x1fe0000
+#define OPRND_MASK_20               0x0100000
+#define OPRND_MASK_20_21            0x0300000
+#define OPRND_MASK_20_22            0x0700000
+#define OPRND_MASK_20_23            0x0f00000
+#define OPRND_MASK_20_24            0x1f00000
+#define OPRND_MASK_20_25            0x3f00000
 #define OPRND_MASK_21_24            0x1e00000
 #define OPRND_MASK_21_25            0x3e00000
 #define OPRND_MASK_25               0x2000000
 #define OPRND_MASK_RSV              0xffffffff
+#define OPRND_MASK_0_3or5_8         OPRND_MASK_0_3 | OPRND_MASK_5_8
+#define OPRND_MASK_0_3or6_7         OPRND_MASK_0_3 | OPRND_MASK_6_7
 #define OPRND_MASK_0_3or21_24       OPRND_MASK_0_3 | OPRND_MASK_21_24
+#define OPRND_MASK_0_3or25          OPRND_MASK_0_3 | OPRND_MASK_25
+#define OPRND_MASK_0_4or21_24       OPRND_MASK_0_4 | OPRND_MASK_21_24
 #define OPRND_MASK_0_4or21_25       OPRND_MASK_0_4 | OPRND_MASK_21_25
 #define OPRND_MASK_0_4or16_20       OPRND_MASK_0_4 | OPRND_MASK_16_20
 #define OPRND_MASK_0_4or8_10        OPRND_MASK_0_4 | OPRND_MASK_8_10
 #define OPRND_MASK_0_4or8_9         OPRND_MASK_0_4 | OPRND_MASK_8_9
 #define OPRND_MASK_0_14or16_20      OPRND_MASK_0_14 | OPRND_MASK_16_20
 #define OPRND_MASK_4or5_8           OPRND_MASK_4   | OPRND_MASK_5_8
+#define OPRND_MASK_5or20_21         OPRND_MASK_5   | OPRND_MASK_20_21
+#define OPRND_MASK_5or20_22         OPRND_MASK_5   | OPRND_MASK_20_22
+#define OPRND_MASK_5or20_23         OPRND_MASK_5   | OPRND_MASK_20_23
+#define OPRND_MASK_5or20_24         OPRND_MASK_5   | OPRND_MASK_20_24
+#define OPRND_MASK_5or20_25         OPRND_MASK_5   | OPRND_MASK_20_25
 #define OPRND_MASK_5or21_24         OPRND_MASK_5   | OPRND_MASK_21_24
 #define OPRND_MASK_2_5or6_9         OPRND_MASK_2_5 | OPRND_MASK_6_9
 #define OPRND_MASK_4_6or21_25       OPRND_MASK_4_6 | OPRND_MASK_21_25
@@ -372,10 +398,23 @@ struct csky_opcode
 #define OPRND_MASK_5_6or21_25       OPRND_MASK_5_6 | OPRND_MASK_21_25
 #define OPRND_MASK_5_7or8_10        OPRND_MASK_5_7 | OPRND_MASK_8_10
 #define OPRND_MASK_5_9or21_25       OPRND_MASK_5_9 | OPRND_MASK_21_25
+#define OPRND_MASK_8_9or21_25       OPRND_MASK_8_9 | OPRND_MASK_21_25
+#define OPRND_MASK_8_9or16_25       OPRND_MASK_8_9 | OPRND_MASK_16_20 | OPRND_MASK_21_25
 #define OPRND_MASK_16_19or21_24     OPRND_MASK_16_19 | OPRND_MASK_21_24
 #define OPRND_MASK_16_20or21_25     OPRND_MASK_16_20 | OPRND_MASK_21_25
 #define OPRND_MASK_4or9_10or25      OPRND_MASK_4 | OPRND_MASK_9_10 | OPRND_MASK_25
 #define OPRND_MASK_4_7or16_24       OPRND_MASK_4_7 | OPRND_MASK_16_20 | OPRND_MASK_21_24
+#define OPRND_MASK_4_6or20          OPRND_MASK_4_6 | OPRND_MASK_20
+#define OPRND_MASK_5_7or20          OPRND_MASK_5_7 | OPRND_MASK_20
+#define OPRND_MASK_4_5or20or25      OPRND_MASK_4 | OPRND_MASK_5 | OPRND_MASK_20 | OPRND_MASK_25
+#define OPRND_MASK_4_6or20or25      OPRND_MASK_4_6 | OPRND_MASK_20 | OPRND_MASK_25
+#define OPRND_MASK_4_7or20or25      OPRND_MASK_4_7 | OPRND_MASK_20 | OPRND_MASK_25
+#define OPRND_MASK_6_9or17_24       OPRND_MASK_6_9 | OPRND_MASK_17_24
+#define OPRND_MASK_6_7or20          OPRND_MASK_6_7 | OPRND_MASK_20
+#define OPRND_MASK_6or20            OPRND_MASK_6 | OPRND_MASK_20
+#define OPRND_MASK_7or20            OPRND_MASK_7 | OPRND_MASK_20
+#define OPRND_MASK_5or8_9or16_25    OPRND_MASK_5 | OPRND_MASK_8_9or16_25
+#define OPRND_MASK_5or8_9or20_25    OPRND_MASK_5 | OPRND_MASK_8_9 | OPRND_MASK_20_25
 
 #define OPERAND_INFO(mask, type, shift) \
   {OPRND_MASK_##mask, OPRND_TYPE_##type, shift}
@@ -8092,6 +8131,2005 @@ const struct csky_opcode csky_v2_opcodes[] =
 			(21_24, VREG, OPRND_SHIFT_0_BIT)),
 	  CSKY_ISA_VDSP),
 
+#define OPRND_SHIFT0(mask, type) (mask, type, OPRND_SHIFT_0_BIT)
+#define OPRND_SHIFT1(mask, type) (mask, type, OPRND_SHIFT_1_BIT)
+#define OPRND_SHIFT2(mask, type) (mask, type, OPRND_SHIFT_2_BIT)
+#define OPRND_SHIFT3(mask, type) (mask, type, OPRND_SHIFT_3_BIT)
+#define OPRND_SHIFT4(mask, type) (mask, type, OPRND_SHIFT_4_BIT)
+
+/* The followings are 860 floating instructions.  */
+    OP32 ("fadd.16",
+	  OPCODE_INFO3 (0xf400c800,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("faddh",
+	  OPCODE_INFO3 (0xf400c800,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsub.16",
+	  OPCODE_INFO3 (0xf400c820,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsubh",
+	  OPCODE_INFO3 (0xf400c820,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmov.16",
+	  OPCODE_INFO2 (0xf400c880,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmovh",
+	  OPCODE_INFO2 (0xf400c880,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fabs.16",
+	  OPCODE_INFO2 (0xf400c8c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fabsh",
+	  OPCODE_INFO2 (0xf400c8c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fneg.16",
+	  OPCODE_INFO2 (0xf400c8e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnegh",
+	  OPCODE_INFO2 (0xf400c8e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphsz.16",
+	  OPCODE_INFO1 (0xf400c900,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzhsh",
+	  OPCODE_INFO1 (0xf400c900,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpltz.16",
+	  OPCODE_INFO1 (0xf400c920,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzlth",
+	  OPCODE_INFO1 (0xf400c920,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpnez.16",
+	  OPCODE_INFO1 (0xf400c940,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzneh",
+	  OPCODE_INFO1 (0xf400c940,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuoz.16",
+	  OPCODE_INFO1 (0xf400c960,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzuoh",
+	  OPCODE_INFO1 (0xf400c960,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphs.16",
+	  OPCODE_INFO2 (0xf400c980,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphsh",
+	  OPCODE_INFO2 (0xf400c980,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmplt.16",
+	  OPCODE_INFO2 (0xf400c9a0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpne.16",
+	  OPCODE_INFO2 (0xf400c9c0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpneh",
+	  OPCODE_INFO2 (0xf400c9c0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuo.16",
+	  OPCODE_INFO2 (0xf400c9e0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuoh",
+	  OPCODE_INFO2 (0xf400c9e0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmaxnm.16",
+	  OPCODE_INFO3 (0xf400cd00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fminnm.16",
+	  OPCODE_INFO3 (0xf400cd20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphz.16",
+	  OPCODE_INFO1 (0xf400cd40,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmplsz.16",
+	  OPCODE_INFO1 (0xf400cd60,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmul.16",
+	  OPCODE_INFO3 (0xf400ca00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmulh",
+	  OPCODE_INFO3 (0xf400ca00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmul.16",
+	  OPCODE_INFO3 (0xf400ca20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmulh",
+	  OPCODE_INFO3 (0xf400ca20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmula.16",
+	  OPCODE_INFO3 (0xf400ca80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmach",
+	  OPCODE_INFO3 (0xf400ca80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmuls.16",
+	  OPCODE_INFO3 (0xf400caa0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmsch",
+	  OPCODE_INFO3 (0xf400caa0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmuls.16",
+	  OPCODE_INFO3 (0xf400cac0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmach",
+	  OPCODE_INFO3 (0xf400cac0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmula.16",
+	  OPCODE_INFO3 (0xf400cae0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmsch",
+	  OPCODE_INFO3 (0xf400cae0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffmula.16",
+	  OPCODE_INFO3 (0xf400ce00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffmuls.16",
+	  OPCODE_INFO3 (0xf400ce20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffnmula.16",
+	  OPCODE_INFO3 (0xf400ce40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffnmuls.16",
+	  OPCODE_INFO3 (0xf400ce60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdivh",
+	  OPCODE_INFO3 (0xf400cb00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdiv.16",
+	  OPCODE_INFO3 (0xf400cb00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("freciph",
+	  OPCODE_INFO2 (0xf400cb20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("frecip.16",
+	  OPCODE_INFO2 (0xf400cb20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsqrt.16",
+	  OPCODE_INFO2 (0xf400cb40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsqrth",
+	  OPCODE_INFO2 (0xf400cb40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsel.16",
+	  OPCODE_INFO3 (0xf400cf20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+  /* Single floating.  */
+    OP32 ("fadd.32",
+	  OPCODE_INFO3 (0xf4000000,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fadds",
+	  OPCODE_INFO3 (0xf4000000,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsub.32",
+	  OPCODE_INFO3 (0xf4000020,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsubs",
+	  OPCODE_INFO3 (0xf4000020,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmov.32",
+	  OPCODE_INFO2 (0xf4000080,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmovs",
+	  OPCODE_INFO2 (0xf4000080,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fabs.32",
+	  OPCODE_INFO2 (0xf40000c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fabss",
+	  OPCODE_INFO2 (0xf40000c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fneg.32",
+	  OPCODE_INFO2 (0xf40000e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnegs",
+	  OPCODE_INFO2 (0xf40000e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphsz.32",
+	  OPCODE_INFO1 (0xf4000100,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzhss",
+	  OPCODE_INFO1 (0xf4000100,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpltz.32",
+	  OPCODE_INFO1 (0xf4000120,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzlts",
+	  OPCODE_INFO1 (0xf4000120,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpnez.32",
+	  OPCODE_INFO1 (0xf4000140,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpznes",
+	  OPCODE_INFO1 (0xf4000140,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuoz.32",
+	  OPCODE_INFO1 (0xf4000160,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzuos",
+	  OPCODE_INFO1 (0xf4000160,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphs.32",
+	  OPCODE_INFO2 (0xf4000180,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphss",
+	  OPCODE_INFO2 (0xf4000180,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmplt.32",
+	  OPCODE_INFO2 (0xf40001a0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmplts",
+	  OPCODE_INFO2 (0xf40001a0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpne.32",
+	  OPCODE_INFO2 (0xf40001c0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpnes",
+	  OPCODE_INFO2 (0xf40001c0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuo.32",
+	  OPCODE_INFO2 (0xf40001e0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuos",
+	  OPCODE_INFO2 (0xf40001e0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmaxnm.32",
+	  OPCODE_INFO3 (0xf4000500,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fminnm.32",
+	  OPCODE_INFO3 (0xf4000520,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphz.32",
+	  OPCODE_INFO1 (0xf4000540,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmplsz.32",
+	  OPCODE_INFO1 (0xf4000560,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmul.32",
+	  OPCODE_INFO3 (0xf4000200,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmuls",
+	  OPCODE_INFO3 (0xf4000200,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmul.32",
+	  OPCODE_INFO3 (0xf4000220,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmuls",
+	  OPCODE_INFO3 (0xf4000220,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmula.32",
+	  OPCODE_INFO3 (0xf4000280,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmacs",
+	  OPCODE_INFO3 (0xf4000280,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmuls.32",
+	  OPCODE_INFO3 (0xf40002a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmscs",
+	  OPCODE_INFO3 (0xf40002a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmuls.32",
+	  OPCODE_INFO3 (0xf40002c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmacs",
+	  OPCODE_INFO3 (0xf40002c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmula.32",
+	  OPCODE_INFO3 (0xf40002e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmscs",
+	  OPCODE_INFO3 (0xf40002e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffmula.32",
+	  OPCODE_INFO3 (0xf4000600,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffmuls.32",
+	  OPCODE_INFO3 (0xf4000620,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffnmula.32",
+	  OPCODE_INFO3 (0xf4000640,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffnmuls.32",
+	  OPCODE_INFO3 (0xf4000660,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdiv.32",
+	  OPCODE_INFO3 (0xf4000300,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdivs",
+	  OPCODE_INFO3 (0xf4000300,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("frecip.32",
+	  OPCODE_INFO2 (0xf4000320,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("frecips",
+	  OPCODE_INFO2 (0xf4000320,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsqrt.32",
+	  OPCODE_INFO2 (0xf4000340,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsqrts",
+	  OPCODE_INFO2 (0xf4000340,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsel.32",
+	  OPCODE_INFO3 (0xf4000720,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+  /* Double floating.  */
+    OP32 ("fadd.64",
+	  OPCODE_INFO3 (0xf4000800,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("faddd",
+	  OPCODE_INFO3 (0xf4000800,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsub.64",
+	  OPCODE_INFO3 (0xf4000820,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsubd",
+	  OPCODE_INFO3 (0xf4000820,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmov.64",
+	  OPCODE_INFO2 (0xf4000880,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmovd",
+	  OPCODE_INFO2 (0xf4000880,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmovx.32",
+	  OPCODE_INFO2 (0xf40008a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fabs.64",
+	  OPCODE_INFO2 (0xf40008c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fabsd",
+	  OPCODE_INFO2 (0xf40008c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fneg.64",
+	  OPCODE_INFO2 (0xf40008e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnegd",
+	  OPCODE_INFO2 (0xf40008e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphsz.64",
+	  OPCODE_INFO1 (0xf4000900,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzhsd",
+	  OPCODE_INFO1 (0xf4000900,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpltz.64",
+	  OPCODE_INFO1 (0xf4000920,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzltd",
+	  OPCODE_INFO1 (0xf4000920,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpnez.64",
+	  OPCODE_INFO1 (0xf4000940,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzned",
+	  OPCODE_INFO1 (0xf4000940,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuoz.64",
+	  OPCODE_INFO1 (0xf4000960,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpzuod",
+	  OPCODE_INFO1 (0xf4000960,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphs.64",
+	  OPCODE_INFO2 (0xf4000980,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphsd",
+	  OPCODE_INFO2 (0xf4000980,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmplt.64",
+	  OPCODE_INFO2 (0xf40009a0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpltd",
+	  OPCODE_INFO2 (0xf40009a0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpne.64",
+	  OPCODE_INFO2 (0xf40009c0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpned",
+	  OPCODE_INFO2 (0xf40009c0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuo.64",
+	  OPCODE_INFO2 (0xf40009e0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmpuod",
+	  OPCODE_INFO2 (0xf40009e0,
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmaxnm.64",
+	  OPCODE_INFO3 (0xf4000d00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fminnm.64",
+	  OPCODE_INFO3 (0xf4000d20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmphz.64",
+	  OPCODE_INFO1 (0xf4000d40,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fcmplsz.64",
+	  OPCODE_INFO1 (0xf4000d60,
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmul.64",
+	  OPCODE_INFO3 (0xf4000a00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmuld",
+	  OPCODE_INFO3 (0xf4000a00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmul.64",
+	  OPCODE_INFO3 (0xf4000a20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmuld",
+	  OPCODE_INFO3 (0xf4000a20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmula.64",
+	  OPCODE_INFO3 (0xf4000a80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmacd",
+	  OPCODE_INFO3 (0xf4000a80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmuls.64",
+	  OPCODE_INFO3 (0xf4000aa0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmscd",
+	  OPCODE_INFO3 (0xf4000aa0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmuls.64",
+	  OPCODE_INFO3 (0xf4000ac0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmacd",
+	  OPCODE_INFO3 (0xf4000ac0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmula.64",
+	  OPCODE_INFO3 (0xf4000ae0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmscd",
+	  OPCODE_INFO3 (0xf4000ae0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffmula.64",
+	  OPCODE_INFO3 (0xf4000e00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffmuls.64",
+	  OPCODE_INFO3 (0xf4000e20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffnmula.64",
+	  OPCODE_INFO3 (0xf4000e40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("ffnmuls.64",
+	  OPCODE_INFO3 (0xf4000e60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdiv.64",
+	  OPCODE_INFO3 (0xf4000b00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdivd",
+	  OPCODE_INFO3 (0xf4000b00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("frecip.64",
+	  OPCODE_INFO2 (0xf4000b20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("frecipd",
+	  OPCODE_INFO2 (0xf4000b20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsqrt.64",
+	  OPCODE_INFO2 (0xf4000b40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsqrtd",
+	  OPCODE_INFO2 (0xf4000b40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fins.32",
+	  OPCODE_INFO2 (0xf4000360,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsel.64",
+	  OPCODE_INFO3 (0xf4000f20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+  /* SIMD floating.  */
+    OP32 ("fadd.f32",
+	  OPCODE_INFO3 (0xf4001000,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("faddm",
+	  OPCODE_INFO3 (0xf4001000,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsub.f32",
+	  OPCODE_INFO3 (0xf4001020,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsubm",
+	  OPCODE_INFO3 (0xf4001020,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmov.f32",
+	  OPCODE_INFO2 (0xf4001080,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmovm",
+	  OPCODE_INFO2 (0xf4001080,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fabs.f32",
+	  OPCODE_INFO2 (0xf40010c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fabsm",
+	  OPCODE_INFO2 (0xf40010c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fneg.f32",
+	  OPCODE_INFO2 (0xf40010e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnegm",
+	  OPCODE_INFO2 (0xf40010e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmul.f32",
+	  OPCODE_INFO3 (0xf4001200,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmulm",
+	  OPCODE_INFO3 (0xf4001200,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmula.f32",
+	  OPCODE_INFO3 (0xf4001280,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmuls.f32",
+	  OPCODE_INFO3 (0xf40012c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fnmacm",
+	  OPCODE_INFO3 (0xf40012c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG),
+			OPRND_SHIFT0 (21_25, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+  /* floating formate.  */
+    OP32 ("fftoi.f32.s32.rn",
+	  OPCODE_INFO2 (0xf4001800,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstosi.rn",
+	  OPCODE_INFO2 (0xf4001800,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.s32.rz",
+	  OPCODE_INFO2 (0xf4001820,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstosi.rz",
+	  OPCODE_INFO2 (0xf4001820,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.s32.rpi",
+	  OPCODE_INFO2 (0xf4001840,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstosi.rpi",
+	  OPCODE_INFO2 (0xf4001840,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.s32.rni",
+	  OPCODE_INFO2 (0xf4001860,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstosi.rni",
+	  OPCODE_INFO2 (0xf4001860,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.u32.rn",
+	  OPCODE_INFO2 (0xf4001880,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstoui.rn",
+	  OPCODE_INFO2 (0xf4001880,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.u32.rz",
+	  OPCODE_INFO2 (0xf40018a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstoui.rz",
+	  OPCODE_INFO2 (0xf40018a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.u32.rpi",
+	  OPCODE_INFO2 (0xf40018c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstoui.rpi",
+	  OPCODE_INFO2 (0xf40018c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.u32.rni",
+	  OPCODE_INFO2 (0xf40018e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstoui.rni",
+	  OPCODE_INFO2 (0xf40018e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.s32.rn",
+	  OPCODE_INFO2 (0xf4001900,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtosi.rn",
+	  OPCODE_INFO2 (0xf4001900,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.s32.rz",
+	  OPCODE_INFO2 (0xf4001920,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtosi.rz",
+	  OPCODE_INFO2 (0xf4001920,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.s32.rpi",
+	  OPCODE_INFO2 (0xf4001940,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtosi.rpi",
+	  OPCODE_INFO2 (0xf4001940,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.s32.rni",
+	  OPCODE_INFO2 (0xf4001960,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtosi.rni",
+	  OPCODE_INFO2 (0xf4001960,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.u32.rn",
+	  OPCODE_INFO2 (0xf4001980,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtoui.rn",
+	  OPCODE_INFO2 (0xf4001980,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.u32.rz",
+	  OPCODE_INFO2 (0xf40019a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtoui.rz",
+	  OPCODE_INFO2 (0xf40019a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.u32.rpi",
+	  OPCODE_INFO2 (0xf40019c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtoui.rpi",
+	  OPCODE_INFO2 (0xf40019c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.u32.rni",
+	  OPCODE_INFO2 (0xf40019e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtoui.rni",
+	  OPCODE_INFO2 (0xf40019e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.s32.rn",
+	  OPCODE_INFO2 (0xf4001c00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtosi.rn",
+	  OPCODE_INFO2 (0xf4001c00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.s32.rz",
+	  OPCODE_INFO2 (0xf4001c20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtosi.rz",
+	  OPCODE_INFO2 (0xf4001c20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.s32.rpi",
+	  OPCODE_INFO2 (0xf4001c40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtosi.rpi",
+	  OPCODE_INFO2 (0xf4001c40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.s32.rni",
+	  OPCODE_INFO2 (0xf4001c60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtosi.rni",
+	  OPCODE_INFO2 (0xf4001c60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.u32.rn",
+	  OPCODE_INFO2 (0xf4001c80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtoui.rn",
+	  OPCODE_INFO2 (0xf4001c80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.u32.rz",
+	  OPCODE_INFO2 (0xf4001ca0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtoui.rz",
+	  OPCODE_INFO2 (0xf4001ca0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.u32.rpi",
+	  OPCODE_INFO2 (0xf4001cc0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtoui.rpi",
+	  OPCODE_INFO2 (0xf4001cc0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.u32.rni",
+	  OPCODE_INFO2 (0xf4001ce0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtoui.rni",
+	  OPCODE_INFO2 (0xf4001ce0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtos",
+	  OPCODE_INFO2 (0xf4001a40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fhtos.f16",
+	  OPCODE_INFO2 (0xf4001a40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstoh",
+	  OPCODE_INFO2 (0xf4001a60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstoh.f32",
+	  OPCODE_INFO2 (0xf4001a60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtos",
+	  OPCODE_INFO2 (0xf4001ac0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fdtos.f64",
+	  OPCODE_INFO2 (0xf4001ac0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fstod",
+	  OPCODE_INFO2 (0xf4001ae0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmfvrh",
+	  OPCODE_INFO2 (0xf4001b00,
+			OPRND_SHIFT0 (0_4, AREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmfvr.32.1",
+	  OPCODE_INFO2 (0xf4001b20,
+			OPRND_SHIFT0 (0_4, AREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmfvrl",
+	  OPCODE_INFO2 (0xf4001b20,
+			OPRND_SHIFT0 (0_4, AREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmtvr.16",
+	  OPCODE_INFO2 (0xf4001fa0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, AREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmfvr.16",
+	  OPCODE_INFO2 (0xf4001f20,
+			OPRND_SHIFT0 (0_4, AREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmtvrh",
+	  OPCODE_INFO2 (0xf4001b40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, AREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmtvr.32.1",
+	  OPCODE_INFO2 (0xf4001b60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, AREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmtvrl",
+	  OPCODE_INFO2 (0xf4001b60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, AREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmtvr.64",
+	  OPCODE_INFO3 (0xf4001f80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, AREG),
+			OPRND_SHIFT0 (21_25, AREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmfvr.64",
+	  OPCODE_INFO3 (0xf4001f00,
+			OPRND_SHIFT0 (0_4, AREG),
+			OPRND_SHIFT0 (21_25, AREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmtvr.32.2",
+	  OPCODE_INFO3 (0xf4001fc0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, AREG),
+			OPRND_SHIFT0 (21_25, AREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fmfvr.32.2",
+	  OPCODE_INFO3 (0xf4001f40,
+			OPRND_SHIFT0 (0_4, AREG),
+			OPRND_SHIFT0 (21_25, AREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    /* flsu.  */
+    OP32 ("fld.16",
+	  SOPCODE_INFO2 (0xf4002300,
+			 (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(4_7or21_24,
+					 IMM_FLDST,
+					 OPRND_SHIFT_1_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldh",
+	  SOPCODE_INFO2 (0xf4002300,
+			 (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(4_7or21_24,
+					 IMM_FLDST,
+					 OPRND_SHIFT_1_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fst.16",
+		    SOPCODE_INFO2 (0xf4002700,
+				   (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (4_7or21_24,
+						   IMM_FLDST,
+						   OPRND_SHIFT_1_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fsth",
+		    SOPCODE_INFO2 (0xf4002700,
+				   (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (4_7or21_24,
+						   IMM_FLDST,
+						   OPRND_SHIFT_1_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldr16",
+	  SOPCODE_INFO2 (0xf4002b00,
+			 (0_4, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(5_6or21_25,
+					 AREG_WITH_LSHIFT_FPU,
+					 OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldrh",
+	  SOPCODE_INFO2 (0xf4002b00,
+			 (0_4, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(5_6or21_25,
+					 AREG_WITH_LSHIFT_FPU,
+					 OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstr.16",
+		    SOPCODE_INFO2 (0xf4002f00,
+				   (0_4, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (5_6or21_25,
+						   AREG_WITH_LSHIFT_FPU,
+						   OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60,
+	  float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstrh",
+		    SOPCODE_INFO2 (0xf4002f00,
+				   (0_4, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (5_6or21_25,
+						   AREG_WITH_LSHIFT_FPU,
+						   OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60,
+	  float_work_fpuv3_fstore),
+    OP32 ("fldm.16",
+	  OPCODE_INFO2 (0xf4003300,
+			(0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
+			(16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldmh",
+	  OPCODE_INFO2 (0xf4003300,
+			(0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
+			(16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstm.16",
+		    OPCODE_INFO2 (0xf4003700,
+				  (0_4or21_24,
+				   FREGLIST_DASH,
+				   OPRND_SHIFT_0_BIT),
+				  (16_20,
+				   AREG_WITH_BRACKET,
+				   OPRND_SHIFT_0_BIT)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstmh",
+		    OPCODE_INFO2 (0xf4003700,
+				  (0_4or21_24,
+				   FREGLIST_DASH,
+				   OPRND_SHIFT_0_BIT),
+				  (16_20,
+				   AREG_WITH_BRACKET,
+				   OPRND_SHIFT_0_BIT)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldmu.16",
+	  OPCODE_INFO2 (0xf4003380,
+			OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldmu.h",
+	  OPCODE_INFO2 (0xf4003380,
+			OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstmu.16",
+		    OPCODE_INFO2 (0xf4003780,
+				  OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstmu.h",
+		    OPCODE_INFO2 (0xf4003780,
+				  OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		   CSKY_ISA_FLOAT_7E60,
+		   float_work_fpuv3_fstore),
+    OP32 ("fld.32",
+	  SOPCODE_INFO2 (0xf4002000,
+			 (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(4_7or21_24,
+					 IMM_FLDST,
+					 OPRND_SHIFT_2_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("flds",
+	  SOPCODE_INFO2 (0xf4002000,
+			 (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(4_7or21_24,
+					 IMM_FLDST,
+					 OPRND_SHIFT_2_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fst.32",
+		    SOPCODE_INFO2 (0xf4002400,
+				   (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (4_7or21_24,
+						   IMM_FLDST,
+						   OPRND_SHIFT_2_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fsts",
+		    SOPCODE_INFO2 (0xf4002400,
+				   (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (4_7or21_24,
+						   IMM_FLDST,
+						   OPRND_SHIFT_2_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldr.32",
+	  SOPCODE_INFO2 (0xf4002800,
+			 (0_4, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(5_6or21_25,
+					 AREG_WITH_LSHIFT_FPU,
+					 OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldrs",
+	  SOPCODE_INFO2 (0xf4002800,
+			 (0_4, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(5_6or21_25,
+					 AREG_WITH_LSHIFT_FPU,
+					 OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstr.32",
+		    SOPCODE_INFO2 (0xf4002c00,
+				   (0_4, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (5_6or21_25,
+						   AREG_WITH_LSHIFT_FPU,
+						   OPRND_SHIFT_0_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstrs",
+		    SOPCODE_INFO2 (0xf4002c00,
+				   (0_4, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (5_6or21_25,
+						   AREG_WITH_LSHIFT_FPU,
+						   OPRND_SHIFT_0_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldm.32",
+	  OPCODE_INFO2 (0xf4003000,
+			OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldms",
+	  OPCODE_INFO2 (0xf4003000,
+			OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstm.32",
+		    OPCODE_INFO2 (0xf4003400,
+				  OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstms",
+		    OPCODE_INFO2 (0xf4003400,
+				  OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldmu.32",
+	  OPCODE_INFO2 (0xf4003080,
+			OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldmu.s",
+	  OPCODE_INFO2 (0xf4003080,
+			OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstmu.32",
+		    OPCODE_INFO2 (0xf4003480,
+				  OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstmu.s",
+		    OPCODE_INFO2 (0xf4003480,
+				  OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fld.64",
+	  SOPCODE_INFO2 (0xf4002100,
+			 (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(4_7or21_24,
+					 IMM_FLDST,
+					 OPRND_SHIFT_2_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldd",
+	  SOPCODE_INFO2 (0xf4002100,
+			 (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(4_7or21_24,
+					 IMM_FLDST,
+					 OPRND_SHIFT_2_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fst.64",
+		    SOPCODE_INFO2 (0xf4002500,
+				   (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (4_7or21_24,
+						   IMM_FLDST,
+						   OPRND_SHIFT_2_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstd",
+		    SOPCODE_INFO2 (0xf4002500,
+				   (0_3or25, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (4_7or21_24,
+						   IMM_FLDST,
+						   OPRND_SHIFT_2_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldr.64",
+	  SOPCODE_INFO2 (0xf4002900,
+			 (0_4, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(5_6or21_25,
+					 AREG_WITH_LSHIFT_FPU,
+					 OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldrd",
+	  SOPCODE_INFO2 (0xf4002900,
+			 (0_4, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(5_6or21_25,
+					 AREG_WITH_LSHIFT_FPU,
+					 OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstr.64",
+		    SOPCODE_INFO2 (0xf4002d00,
+				   (0_4, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (5_6or21_25,
+						   AREG_WITH_LSHIFT_FPU,
+						   OPRND_SHIFT_0_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstrd",
+		    SOPCODE_INFO2 (0xf4002d00,
+				   (0_4, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (5_6or21_25,
+						   AREG_WITH_LSHIFT_FPU,
+						   OPRND_SHIFT_0_BIT))),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldm.64",
+	  OPCODE_INFO2 (0xf4003100,
+			OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldmd",
+	  OPCODE_INFO2 (0xf4003100,
+			OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstm.64",
+		    OPCODE_INFO2 (0xf4003500,
+				  OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstmd",
+		    OPCODE_INFO2 (0xf4003500,
+				  OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldmu.64",
+	  OPCODE_INFO2 (0xf4003180,
+			OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fldmu.d",
+	  OPCODE_INFO2 (0xf4003180,
+			OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+			OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstmu.64",
+		    OPCODE_INFO2 (0xf4003580,
+				  OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32_WITH_WORK ("fstmu.d",
+		    OPCODE_INFO2 (0xf4003580,
+				  OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH),
+				  OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fldrm",
+	  SOPCODE_INFO2 (0xf4002a00,
+			 (0_4, FREG, OPRND_SHIFT_0_BIT),
+			 BRACKET_OPRND ((16_20,
+					 AREG,
+					 OPRND_SHIFT_0_BIT),
+					(5_6or21_25,
+					 AREG_WITH_LSHIFT_FPU,
+					 OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstrm",
+		    SOPCODE_INFO2 (0xf4002e00,
+				   (0_4, FREG, OPRND_SHIFT_0_BIT),
+				   BRACKET_OPRND ((16_20,
+						   AREG,
+						   OPRND_SHIFT_0_BIT),
+						  (5_6or21_25,
+						   AREG_WITH_LSHIFT_FPU,
+						   OPRND_SHIFT_0_BIT))),
+	  CSKY_ISA_FLOAT_7E60,
+	  float_work_fpuv3_fstore),
+    OP32 ("fldmm",
+	  OPCODE_INFO2 (0xf4003200,
+			(0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
+			(16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32_WITH_WORK ("fstmm",
+		    OPCODE_INFO2 (0xf4003600,
+				  (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
+				  (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)),
+		    CSKY_ISA_FLOAT_7E60,
+		    float_work_fpuv3_fstore),
+    OP32 ("fftox.f16.u16",
+	  OPCODE_INFO2 (0xf4004000,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftox.f16.s16",
+	  OPCODE_INFO2 (0xf4004020,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftox.f16.u32",
+	  OPCODE_INFO2 (0xf4004100,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftox.f16.s32",
+	  OPCODE_INFO2 (0xf4004120,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftox.f32.u32",
+	  OPCODE_INFO2 (0xf4004140,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftox.f32.s32",
+	  OPCODE_INFO2 (0xf4004160,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftox.f64.u32",
+	  OPCODE_INFO2 (0xf4004180,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftox.f64.s32",
+	  OPCODE_INFO2 (0xf40041a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fxtof.u16.f16",
+	  OPCODE_INFO2 (0xf4004800,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fxtof.s16.f16",
+	  OPCODE_INFO2 (0xf4004820,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fxtof.u32.f16",
+	  OPCODE_INFO2 (0xf4004900,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fxtof.s32.f16",
+	  OPCODE_INFO2 (0xf4004920,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fxtof.u32.f32",
+	  OPCODE_INFO2 (0xf4004940,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fxtof.s32.f32",
+	  OPCODE_INFO2 (0xf4004960,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fxtof.u32.f64",
+	  OPCODE_INFO2 (0xf4004980,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fxtof.s32.f64",
+	  OPCODE_INFO2 (0xf40049a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.s16",
+	  OPCODE_INFO2 (0xf4004220,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.u16",
+	  OPCODE_INFO2 (0xf4004200,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.s32",
+	  OPCODE_INFO2 (0xf4004320,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f16.u32",
+	  OPCODE_INFO2 (0xf4004300,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.s32",
+	  OPCODE_INFO2 (0xf4004360,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f32.u32",
+	  OPCODE_INFO2 (0xf4004340,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.s32",
+	  OPCODE_INFO2 (0xf40043a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftoi.f64.u32",
+	  OPCODE_INFO2 (0xf4004380,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fitof.s16.f16",
+	  OPCODE_INFO2 (0xf4004a20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fitof.u16.f16",
+	  OPCODE_INFO2 (0xf4004a00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fitof.s32.f16",
+	  OPCODE_INFO2 (0xf4004b20,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fitof.u32.f16",
+	  OPCODE_INFO2 (0xf4004b00,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fitof.s32.f32",
+	  OPCODE_INFO2 (0xf4004b60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsitos",
+	  OPCODE_INFO2 (0xf4004b60,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fitof.u32.f32",
+	  OPCODE_INFO2 (0xf4004b40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fuitos",
+	  OPCODE_INFO2 (0xf4004b40,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fitof.s32.f64",
+	  OPCODE_INFO2 (0xf4004ba0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fsitod",
+	  OPCODE_INFO2 (0xf4004ba0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fitof.u32.f64",
+	  OPCODE_INFO2 (0xf4004b80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fuitod",
+	  OPCODE_INFO2 (0xf4004b80,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f16.rn",
+	  OPCODE_INFO2 (0xf4004400,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f16.rz",
+	  OPCODE_INFO2 (0xf4004420,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f16.rpi",
+	  OPCODE_INFO2 (0xf4004440,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f16.rni",
+	  OPCODE_INFO2 (0xf4004460,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f32.rn",
+	  OPCODE_INFO2 (0xf4004480,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f32.rz",
+	  OPCODE_INFO2 (0xf40044a0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f32.rpi",
+	  OPCODE_INFO2 (0xf40044c0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f32.rni",
+	  OPCODE_INFO2 (0xf40044e0,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f64.rn",
+	  OPCODE_INFO2 (0xf4004500,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f64.rz",
+	  OPCODE_INFO2 (0xf4004520,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f64.rpi",
+	  OPCODE_INFO2 (0xf4004540,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("fftofi.f64.rni",
+	  OPCODE_INFO2 (0xf4004560,
+			OPRND_SHIFT0 (0_4, FREG),
+			OPRND_SHIFT0 (16_20, FREG)),
+	  CSKY_ISA_FLOAT_7E60),
+    DOP32_WITH_WORK ("fmovi.16",
+		     OPCODE_INFO2 (0xf400e400,
+				   OPRND_SHIFT0 (0_4, FREG),
+				   OPRND_SHIFT0 (5or8_9or16_25, HFLOAT_FMOVI)),
+		     OPCODE_INFO3 (0xf400e400,
+				   OPRND_SHIFT0 (0_4, FREG),
+				   OPRND_SHIFT0 (5or8_9or20_25, IMM9b),
+				   OPRND_SHIFT0 (16_19, IMM4b)),
+		     CSKY_ISA_FLOAT_7E60,
+		     float_work_fpuv3_fmovi),
+    DOP32_WITH_WORK ("fmovi.32",
+		     OPCODE_INFO2 (0xf400e440,
+				   OPRND_SHIFT0 (0_4, FREG),
+				   OPRND_SHIFT0 (5or8_9or16_25, SFLOAT_FMOVI)),
+		     OPCODE_INFO3 (0xf400e440,
+				   OPRND_SHIFT0 (0_4, FREG),
+				   OPRND_SHIFT0 (5or8_9or20_25, IMM9b),
+				   OPRND_SHIFT0 (16_19, IMM4b)),
+		     CSKY_ISA_FLOAT_7E60,
+		     float_work_fpuv3_fmovi),
+    DOP32_WITH_WORK ("fmovi.64",
+		     OPCODE_INFO2 (0xf400e480,
+				   OPRND_SHIFT0 (0_4, FREG),
+				   OPRND_SHIFT0 (5or8_9or16_25, DFLOAT_FMOVI)),
+		     OPCODE_INFO3 (0xf400e480,
+				   OPRND_SHIFT0 (0_4, FREG),
+				   OPRND_SHIFT0 (5or8_9or20_25, IMM9b),
+				   OPRND_SHIFT0 (16_19, IMM4b)),
+		     CSKY_ISA_FLOAT_7E60,
+		     float_work_fpuv3_fmovi),
+#undef _RELOC32
+#define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
+    OP32 ("flrw.32",
+	  OPCODE_INFO2 (0xf4003800,
+			(0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			(4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("flrws",
+	  OPCODE_INFO2 (0xf4003800,
+			(0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			(4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("flrw.64",
+	  OPCODE_INFO2 (0xf4003900,
+			(0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			(4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)),
+	  CSKY_ISA_FLOAT_7E60),
+    OP32 ("flrwd",
+	  OPCODE_INFO2 (0xf4003900,
+			(0_3or25, FREG, OPRND_SHIFT_0_BIT),
+			(4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)),
+	  CSKY_ISA_FLOAT_7E60),
+#undef _RELOC32
+#define _RELOC32 0
+
     /* The following are aliases for other instructions.  */
     /* setc -> cmphs r0, r0  */
     OP16 ("setc",
@@ -8239,5 +10277,6 @@ const struct csky_opcode csky_v2_opcodes[] =
 	   OPCODE_INFO1 (0xc4007c40,
 			 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)),
 	   CSKYV2_ISA_1E2),
+
     {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL}
   };
author	Cooper Qu <cooper.qu@linux.alibaba.com>	2020-09-07 17:24:11 +0800
committer	Lifang Xia <lifang_xia@c-sky.com>	2020-09-09 19:25:40 +0800
commit	1feede9b384ef80a268ffe0b18e75bd60574f7c7 (patch)
tree	2981852750a2405cc1cdf1cfade31ca5d7574ba0
parent	dfbee68088e822453fdc82f6b8a3a5bc468944b1 (diff)
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