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| author | Nelson Chu <nelson@rivosinc.com> | 2023-09-01 15:21:35 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-09-01 15:37:59 +0800 |
| commit | 12e70a6d0c3550e8eec9f9a0a7abb8bae49fc097 (patch) | |
| tree | 0df35a750c4673933164ea9b827c71379cddc09e | |
| parent | 8ba212f8933df0560d600d14c032be251aa21a71 (diff) | |
| download | binutils-12e70a6d0c3550e8eec9f9a0a7abb8bae49fc097.zip binutils-12e70a6d0c3550e8eec9f9a0a7abb8bae49fc097.tar.gz binutils-12e70a6d0c3550e8eec9f9a0a7abb8bae49fc097.tar.bz2 | |
RISC-V: Fixed the wrong expansion for pseudo vmsge[u].vx instructions.
The original report was from Kiva Oyama <libkernelpanic@gmail.com>,
https://sourceware.org/pipermail/binutils/2023-August/129255.html
The vmsge[u].vx pseudo should be expanded to masked vmslt[u].vx only when
vd != v0. Otherwise, it should be expanded to unmasked one.
gas/
* config/tc-riscv.c (vector_macro): Fixed the wrong expansion for
pseudo vmsge[u].vx instructions.
* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Updated.
| -rw-r--r-- | gas/config/tc-riscv.c | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 959cbbc..e49b34f 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1966,13 +1966,13 @@ vector_macro (struct riscv_cl_insn *ip) /* Masked. Have vtemp to avoid overlap constraints. */ if (vd == vm) { - macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, -1); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); } else { /* Preserve the value of vd if not updating by vm. */ - macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, -1); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); @@ -2001,13 +2001,13 @@ vector_macro (struct riscv_cl_insn *ip) /* Masked. Have vtemp to avoid overlap constraints. */ if (vd == vm) { - macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, -1); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); } else { /* Preserve the value of vd if not updating by vm. */ - macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1); + macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vtemp, vs2, vs1, -1); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); diff --git a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d index dcc951a..aa633e3 100644 --- a/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d +++ b/gas/testsuite/gas/riscv/vector-insns-vmsgtvx.d @@ -11,9 +11,9 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4 [ ]+[0-9a-f]+:[ ]+6cc64457[ ]+vmslt.vx[ ]+v8,v12,a2,v0.t [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0 -[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6e85c657[ ]+vmslt.vx[ ]+v12,v8,a1 [ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12 -[ ]+[0-9a-f]+:[ ]+6c85c657[ ]+vmslt.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6e85c657[ ]+vmslt.vx[ ]+v12,v8,a1 [ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12 [ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0 [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4 @@ -21,9 +21,9 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+76422257[ ]+vmnot.m[ ]+v4,v4 [ ]+[0-9a-f]+:[ ]+68c64457[ ]+vmsltu.vx[ ]+v8,v12,a2,v0.t [ ]+[0-9a-f]+:[ ]+6e802457[ ]+vmxor.mm[ ]+v8,v8,v0 -[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6a85c657[ ]+vmsltu.vx[ ]+v12,v8,a1 [ ]+[0-9a-f]+:[ ]+62062057[ ]+vmandn.mm[ ]+v0,v0,v12 -[ ]+[0-9a-f]+:[ ]+6885c657[ ]+vmsltu.vx[ ]+v12,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+6a85c657[ ]+vmsltu.vx[ ]+v12,v8,a1 [ ]+[0-9a-f]+:[ ]+62062657[ ]+vmandn.mm[ ]+v12,v0,v12 [ ]+[0-9a-f]+:[ ]+62402257[ ]+vmandn.mm[ ]+v4,v4,v0 [ ]+[0-9a-f]+:[ ]+6ac22257[ ]+vmor.mm[ ]+v4,v12,v4 |