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| author | Alice Carlotti <alice.carlotti@arm.com> | 2025-10-02 20:45:33 +0100 |
|---|---|---|
| committer | Alice Carlotti <alice.carlotti@arm.com> | 2025-10-10 01:14:06 +0100 |
| commit | 006c5e38097fc562e1b77ace04bd50956f480ed3 (patch) | |
| tree | d4a20350021593f00409d6a210ed60e7d1d8179d | |
| parent | ec159031adedc0dc7c1e56e4bf9688bfcad3a319 (diff) | |
| download | binutils-006c5e38097fc562e1b77ace04bd50956f480ed3.zip binutils-006c5e38097fc562e1b77ace04bd50956f480ed3.tar.gz binutils-006c5e38097fc562e1b77ace04bd50956f480ed3.tar.bz2 | |
aarch64: Allow multiple fields in {ins|ext}_regno
Adjust SME_PNd3/SME_PNg3 to use explicit FLD_CONST_1 bits. This allows
the use of operand specific data to be eliminated here.
| -rw-r--r-- | opcodes/aarch64-asm.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
4 files changed, 7 insertions, 8 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index fafbc4d..bac5dfa 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -104,8 +104,8 @@ aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - int val = info->reg.regno - get_operand_specific_data (self); - insert_field (self->fields[0], code, val, 0); + int val = info->reg.regno; + insert_all_fields (self, code, val); return true; } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index f2683d0..8554cd2 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -295,8 +295,7 @@ aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - info->reg.regno = (extract_field (self->fields[0], code, 0) - + get_operand_specific_data (self)); + info->reg.regno = extract_all_fields (self, code); return true; } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 90cbf8f..18de767 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -301,8 +301,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pdx2}, "a list of SVE predicate registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "a list of SVE predicate registers"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNd3}, "an SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_PNd3}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SVE_Pg3}, "an SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm1_8}, "an indexed SVE predicate-as-counter register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm2_8}, "an indexed SVE predicate-as-counter register"}, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 288134e..1e33e51 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -8080,9 +8080,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a list of SVE predicate registers") \ Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SME_PNd3", 8 << OPD_F_OD_LSB, F(FLD_SME_PNd3), \ + Y(PRED_REG, regno, "SME_PNd3", 0, F(FLD_CONST_1, FLD_SME_PNd3), \ "an SVE predicate-as-counter register") \ - Y(PRED_REG, regno, "SME_PNg3", 8 << OPD_F_OD_LSB, F(FLD_SVE_Pg3), \ + Y(PRED_REG, regno, "SME_PNg3", 0, F(FLD_CONST_1, FLD_SVE_Pg3), \ "an SVE predicate-as-counter register") \ Y(PRED_REG, regno, "SME_PNn", 0, F(FLD_SVE_Pn), \ "an SVE predicate-as-counter register") \ |