| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2023-12-08 | Add misaligned memory access for spike. | Yanzhang Wang | 1 | -1/+2 | |
| The spec does not forbid the misaligned memory access. And the gcc will generate vector load/store to access misaligned memory by default. Currently the QEMU supports this feature, so to support in spike is also make sense. Reference test case: gcc/gcc/testsuite/gcc.dg/vect/vect-align-1.c | |||||
| 2023-11-22 | Fix CI run failure on rv64gc | Pan Li | 1 | -2/+6 | |
| Signed-off-by: Pan Li <pan2.li@intel.com> | |||||
| 2023-11-21 | Inject CPU options to spike run test from elf file | Pan Li | 1 | -6/+7 | |
| * Refactor CPU options for exacting common part between qemu and spike. * Inject CPU options to spike run command line. The below common CPU options are extracted to common part. * xlen * vlen * extensions The above CPU options will be leveraged to build the run arguments for both the qemu and spike, for example. QEMU: qemu-riscv64 -cpu rv64,v=true,vlen=1024,elen=64,vext_spec=v1.0 SPIKE: spike --isa=rv64imafdcv_zicsr_zifencei_zmmul --varch=vlen:1024,elen:64 Signed-off-by: Pan Li <pan2.li@intel.com> | |||||
| 2022-05-23 | Add option '--with-sim' to set simulator | Liaoshihua | 1 | -2/+2 | |
| 2020-11-04 | Support run testsuite with spike | Kito Cheng | 4 | -0/+10 | |
 |
index : riscv-gnu-toolchain.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |