Bump linux header to 5.0

6 files changed, 71 insertions, 28 deletions

diff --git a/linux-headers/include/asm/..install.cmd b/linux-headers/include/asm/..install.cmd
index 86b2f63..403c15c 100644
--- a/linux-headers/include/asm/..install.cmd
+++ b/linux-headers/include/asm/..install.cmd
@@ -1 +1 @@
-cmd_/scratch/palmer/work/20170821-glibc/riscv-gnu-toolchain/linux-headers/include/asm/.install := /bin/sh scripts/headers_install.sh /scratch/palmer/work/20170821-glibc/riscv-gnu-toolchain/linux-headers/include/asm ./arch/riscv/include/uapi/asm siginfo.h auxvec.h elf.h hwcap.h byteorder.h ucontext.h bitsperlong.h ptrace.h sigcontext.h; /bin/sh scripts/headers_install.sh /scratch/palmer/work/20170821-glibc/riscv-gnu-toolchain/linux-headers/include/asm ./arch/riscv/include/generated/uapi/asm sembuf.h fcntl.h resource.h posix_types.h ioctls.h termios.h signal.h msgbuf.h poll.h socket.h termbits.h ipcbuf.h swab.h sockios.h stat.h errno.h mman.h statfs.h param.h unistd.h shmbuf.h ioctl.h setup.h types.h; touch /scratch/palmer/work/20170821-glibc/riscv-gnu-toolchain/linux-headers/include/asm/.install
+cmd_/home/users/kito/riscv-gnu-toolchain-workspace/riscv-gnu-toolchain/linux/install_hdr/include/asm/.install := /bin/sh scripts/headers_install.sh /home/users/kito/riscv-gnu-toolchain-workspace/riscv-gnu-toolchain/linux/install_hdr/include/asm ./arch/riscv/include/uapi/asm ucontext.h byteorder.h elf.h hwcap.h auxvec.h unistd.h bitsperlong.h ptrace.h sigcontext.h; /bin/sh scripts/headers_install.sh /home/users/kito/riscv-gnu-toolchain-workspace/riscv-gnu-toolchain/linux/install_hdr/include/asm ./arch/riscv/include/generated/uapi/asm bpf_perf_event.h sembuf.h fcntl.h errno.h termios.h ipcbuf.h posix_types.h ioctls.h msgbuf.h siginfo.h socket.h termbits.h swab.h sockios.h resource.h stat.h signal.h mman.h statfs.h param.h poll.h shmbuf.h ioctl.h setup.h types.h; touch /home/users/kito/riscv-gnu-toolchain-workspace/riscv-gnu-toolchain/linux/install_hdr/include/asm/.install
diff --git a/linux-headers/include/asm/bpf_perf_event.h b/linux-headers/include/asm/bpf_perf_event.h
new file mode 100644
index 0000000..3097758
--- /dev/null
+++ b/linux-headers/include/asm/bpf_perf_event.h
@@ -0,0 +1 @@
+#include <asm-generic/bpf_perf_event.h>
diff --git a/linux-headers/include/asm/elf.h b/linux-headers/include/asm/elf.h
index 42fd7ff..754cfb5 100644
--- a/linux-headers/include/asm/elf.h
+++ b/linux-headers/include/asm/elf.h
@@ -19,10 +19,18 @@ typedef unsigned long elf_greg_t;
 typedef struct user_regs_struct elf_gregset_t;
 #define ELF_NGREG (sizeof(elf_gregset_t) / sizeof(elf_greg_t))
 
+/* We don't support f without d, or q.  */
+typedef __u64 elf_fpreg_t;
 typedef union __riscv_fp_state elf_fpregset_t;
+#define ELF_NFPREG (sizeof(struct __riscv_d_ext_state) / sizeof(elf_fpreg_t))
 
-#define ELF_RISCV_R_SYM(r_info) ((r_info) >> 32)
-#define ELF_RISCV_R_TYPE(r_info) ((r_info) & 0xffffffff)
+#if __riscv_xlen == 64
+#define ELF_RISCV_R_SYM(r_info)		ELF64_R_SYM(r_info)
+#define ELF_RISCV_R_TYPE(r_info)	ELF64_R_TYPE(r_info)
+#else
+#define ELF_RISCV_R_SYM(r_info)		ELF32_R_SYM(r_info)
+#define ELF_RISCV_R_TYPE(r_info)	ELF32_R_TYPE(r_info)
+#endif
 
 /*
  * RISC-V relocation types
@@ -79,5 +87,12 @@ typedef union __riscv_fp_state elf_fpregset_t;
 #define R_RISCV_TPREL_I		49
 #define R_RISCV_TPREL_S		50
 #define R_RISCV_RELAX		51
+#define R_RISCV_SUB6		52
+#define R_RISCV_SET6		53
+#define R_RISCV_SET8		54
+#define R_RISCV_SET16		55
+#define R_RISCV_SET32		56
+#define R_RISCV_32_PCREL	57
+
 
 #endif /* _ASM_ELF_H */
diff --git a/linux-headers/include/asm/siginfo.h b/linux-headers/include/asm/siginfo.h
index f96849a..0815d29 100644
--- a/linux-headers/include/asm/siginfo.h
+++ b/linux-headers/include/asm/siginfo.h
@@ -1,24 +1 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Copyright (C) 2016 SiFive, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#ifndef __ASM_SIGINFO_H
-#define __ASM_SIGINFO_H
-
-#define __ARCH_SI_PREAMBLE_SIZE	(__SIZEOF_POINTER__ == 4 ? 12 : 16)
-
 #include <asm-generic/siginfo.h>
-
-#endif
diff --git a/linux-headers/include/asm/ucontext.h b/linux-headers/include/asm/ucontext.h
index 041da35..9f983d3 100644
--- a/linux-headers/include/asm/ucontext.h
+++ b/linux-headers/include/asm/ucontext.h
@@ -26,9 +26,19 @@ struct ucontext {
 	struct ucontext	 *uc_link;
 	stack_t		  uc_stack;
 	sigset_t	  uc_sigmask;
-	/* glibc uses a 1024-bit sigset_t */
+	/* There's some padding here to allow sigset_t to be expanded in the
+	 * future.  Though this is unlikely, other architectures put uc_sigmask
+	 * at the end of this structure and explicitly state it can be
+	 * expanded, so we didn't want to box ourselves in here. */
 	__u8		  __unused[1024 / 8 - sizeof(sigset_t)];
-	/* last for future expansion */
+	/* We can't put uc_sigmask at the end of this structure because we need
+	 * to be able to expand sigcontext in the future.  For example, the
+	 * vector ISA extension will almost certainly add ISA state.  We want
+	 * to ensure all user-visible ISA state can be saved and restored via a
+	 * ucontext, so we're putting this at the end in order to allow for
+	 * infinite extensibility.  Since we know this will be extended and we
+	 * assume sigset_t won't be extended an extreme amount, we're
+	 * prioritizing this. */
 	struct sigcontext uc_mcontext;
 };
 
diff --git a/linux-headers/include/asm/unistd.h b/linux-headers/include/asm/unistd.h
index 96bb270..1f3bd3e 100644
--- a/linux-headers/include/asm/unistd.h
+++ b/linux-headers/include/asm/unistd.h
@@ -1 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef __LP64__
+#define __ARCH_WANT_NEW_STAT
+#endif /* __LP64__ */
+
 #include <asm-generic/unistd.h>
+
+/*
+ * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
+ * having a direct 'fence.i' instruction available to userspace (which we
+ * can't trap!), that's not actually viable when running on Linux because the
+ * kernel might schedule a process on another hart.  There is no way for
+ * userspace to handle this without invoking the kernel (as it doesn't know the
+ * thread->hart mappings), so we've defined a RISC-V specific system call to
+ * flush the instruction cache.
+ *
+ * __NR_riscv_flush_icache is defined to flush the instruction cache over an
+ * address range, with the flush applying to either all threads or just the
+ * caller.  We don't currently do anything with the address range, that's just
+ * in there for forwards compatibility.
+ */
+#ifndef __NR_riscv_flush_icache
+#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
+#endif
+__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)