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authorKito Cheng <kito.cheng@sifive.com>2022-12-16 14:46:42 +0800
committerKito Cheng <kito.cheng@sifive.com>2022-12-16 14:47:14 +0800
commitcb8f1a0942dc4195d4d1f0cf353aba69c52d6d93 (patch)
tree0c673afbcd5016878fed988c9f9c6e20f84b8217
parenta4f97aab32d19ba58d5fc45071bf956a35e22942 (diff)
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Add unittest to march-to-cpu-opt
https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1167 has found some bug, and I realized the testing of march-to-cpu-opt is...not well, so spend some time to improve that a little bit, it's not complete testing, but at least it's a start :P
-rwxr-xr-xscripts/march-to-cpu-opt17
1 files changed, 16 insertions, 1 deletions
diff --git a/scripts/march-to-cpu-opt b/scripts/march-to-cpu-opt
index 0f3f08d..60d992a 100755
--- a/scripts/march-to-cpu-opt
+++ b/scripts/march-to-cpu-opt
@@ -2,6 +2,7 @@
import argparse
import sys
+import unittest
EXT_OPTS = {
"zba": "zba=true",
@@ -129,8 +130,22 @@ def conver_arch_to_qemu_cpu_opt(march):
cpu_opt.append(EXT_OPTS[ext])
return ",".join(cpu_opt)
+
+class TestArchStringParse(unittest.TestCase):
+ def _test(self, arch, expected_arch_list, expected_vlen=0):
+ exts = parse_march(arch)
+ vlen = get_vlen(exts)
+ self.assertEqual(expected_vlen, vlen)
+ self.assertEqual(set(expected_arch_list), set(exts.keys()))
+
+ def test_rv64gc(self):
+ self._test("rv64gc", ['i', 'm', 'a', 'f', 'd', 'c'])
+ self._test("rv32imc_zve32x", ['i', 'm', 'c', 'zve32x'], expected_vlen=32)
+ self._test("rv32imc_zve32x_zvl128b", ['i', 'm', 'c', 'zve32x', 'zvl128b'], expected_vlen=128)
+
+
def selftest():
- print(parse_march("rv64gc"))
+ unittest.main(argv=sys.argv[1:])
def main(argv):
opt = parse_opt(argv)